Texas Instruments

Mixed Signal and Analog
Blue Band

MSP430x320 Family, Buglist and add. Informations

Version 4.0 - April 1998 


Packages: FZ=68CLCC (windowed EPROM), PG= 64QFP (ROM/C or OTP/P versions),
                PM= 64QFP (ROM/C or OTP/P versions)
 
 
Ref-#  Comment 
 A4  PUSH #4, PUSH #8 
The single operand instruction does not utilize from the internal constant 4 and 8. 
But the other internal constants (0, 1, 2, -1) are used. The Assembler version 1.08 
produces correct code - two words, the instruction  PUSH and 0004 or 0008. 
Modification: not planned 
 E1  EPROM 
The operating supply voltage is limited to 4.5V - 5.5V 
 F1  FUSE 
The fuse is connected to VCC instead to TDI 
 F2  FUSE 
Fuse is not released for application use 
 J2  JTAG, input path of TDO/TDI 
The input path of the TDO/TDI input is a standard CMOS buffer. Undefined levels 
there can cause additional current consumption from VCC to VSS via the gate. 
Workaround: add an external pull-down resistor that avoids floating node. 
Modification: 
The input buffer of the TDO/TDI input is modified to a gated input and no further 
ext. pull-down is needed in the application. 
 J3 
JTAG, OTP and EPROM devices only 
The input path of the TDI/VPP input is a standard CMOS buffer. Undefined levels 
there can cause additional current consumption from VCC to VSS via the gate. 
Workaround: add an external pull-down resistor that avoids floating node. 
Modification: 
The input buffer of the TDO/TDI input is modified to a gated input and no further 
ext. pull-down is needed in the application. 
 O5 Osc32, lack of reliable operation of the crystal oscillator : 
    The oscillator  works but at 5V operation and temperature below 0oC it can stop 
Workaround: Two 12pF capacitors from XIN and XOUT to VSS 
                           The  workaround may not work correctly on all conitions>> 
                           It needs to be check in the specific application.
 R1 
RST/NMI: Input is slower (ca. 30ns) by adding a Cap. to output of 
the input inverter - NOT to the RST/NMI pin 
 S1 
Interrupt: an interupt flag can be cleared by an interrupt request 
with higher priority if the interrupt with higher priority is requested during 
bus grant cycle in the interrupt request service phase. 
Workaround: none. 
Modification:  bug removed since 

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