| Ref-# |
Comment |
A4
top |
PUSH #4, PUSH #8
The single operand instruction does not utilize from the
internal constant 4 and 8.
But the other internal constants (0, 1, 2, -1) are used.
The Assembler version 1.08
produces correct code - two words, the instruction
PUSH and 0004 or 0008. |
C2
top |
SCG, nominal frequency is not adjusted to center of DCO (tap
13)
* Modification: Adjust nominal frequency to center of DCO (tap 13) |
J2
top |
JTAG, input path of TDO/TDI
The input path of the TDO/TDI input is a standard CMOS
buffer. Undefined levels
there can cause additional current consumption from VCC
to VSS via the gate.
* Workaround: add an external pull-down resistor that avoids floating
node.
* Modification: presently in ROM version only
The input buffer of the TDO/TDI input is modified to a
gated input and no further
ext. pull-down is needed in the application. Valid only
for ROM devices. |
|
|
JTAG, OTP and EPROM devices only
The input path of the TDI/VPP input is a standard CMOS
buffer. Undefined levels
there can cause additional current consumption from VCC
to VSS via the gate.
* Workaround: add an external pull-down resistor that avoids floating
node.
* Modification: not planned. |
L3
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LCD analog levels are wrong or S29 is always switched to CMPI
* Description: A protection diode is switched from S29/O29/CMPI line
to CPON
bit line instead to VCC. This can causes the RS-FlipFlop,
which controls to select
S29/O29/CMPI to CMPI function, to switch to CMPI. Once
the LCD signal or
the O29 level becomes high via the diode the CPON bit
line can be put to high
level even if CPON bit should be low.
S29/O29 signal >----o __
\o----*----<__> S29/O29/CMPI
CMPI signal <----o |
|
+---+
\ /
=====
|
[CPON]
* Workaround: (None). If S29/O29 is not used in the application there is
no impact for
any application. The software should have the instruction
sequence CPON set/CPON reset
eg. bis.b #40h,&04eh // bic.b #40h,&04eh
to ensure CMPI is selected and LCD analog levels are correct.
* Modification: Diode is clamped correctly to VCC. |
|
|
Port P3, select direction of P3.x/TAx
* Description: The direction of P3.3/TA0 to P3.7/TA4 is controlled
by the capture/
compare bit CAPx when P3SEL.x bit is set. If P3SEL.x is
reset,the direction
bit P3DIR.x defines the direction in- or output. In compare
mode the input signal can not
be latched into the capture/compare register bit SCCI.
* Workaround: none.
* Modification: The direction of P3.3/TA0 to P3.7/TA4 is controlled
only by the
P3DIR.x bit. It is not controlled by CAPx bit. |
|
|
Added an internal capacitor between VCC1 and VSS3 |
S3
top |
MSP430P337: poor latch-up protection on RST/NMI . A serial resistor
of 1kOhm is
needed externally on the PWB.
MSP430P337: poor latch-up protection on TDO. No actions needed - no
appl. pin function. |
S4
top |
* MSP430C337: optional Pullup/down resistor at CIN pin
It is not possible to have this option
resistor selected.
* Modification: Enable option correctly. |
TA1
top |
Critical timing for reset of Capture/Compare interrupt flags CCIFGx
* Description: When the interrupt vector word TAIV is read the according
interrupt
flag is reset automatically. This can be left set.
* Workaround: Reset the flag in the interrupt routine by software.
* Modification: The flag is reset correctly. |
TA2
top |
TAIFG
* Description: The TAIFG flag is automatically reset when the vector
word register
TAIV is read. If the Timer Clock remains high it will
be set again. This can
happen when ACLK or external clock TACLK is selected.
* Workaround: Ensure that the high phase of the clock frequency is
short enough
or ensure that the flag is reset properly by software.
* Modification: Works correct independent of the level of Timer Clock. |
TA3
top |
Set CCIFG0 ... CCIFG4, all capture/compare blocks are identical
* Description: The CCIFGx flag set signal is not accepted during an
access of the
software/CPU to the according register CCRx. If the set
signal (one period of the
timer clock) is longer than 1.5/fMCLK, it is always set.
Otherwise it may be set or not.
* Workaround: Modify the according capture/compare register whether
if the timer is
stopped of after the according CCIFGx is set.
* Modification: The CCIFGx flag set signal is temorarily latche to
overcome access situation. |
TA4
top |
Counter increments with writing to TAR register
* Description: If the Timer Clock signal is high and the Timer is loaded
(write to
TAR register), the Timer increments after load is completed
even if the Timer Clock
signal had no count condition.
* Workaround: none.
* Modification: After loading the Timer it starts with the loaded data. |
TA5
top |
CAP = 1: CCIFG is set 180o of the Timer Clock prior to capture data
of TAR into CCR.
* Description: The capture is not done but already the CCRIFG is set!
If the
Timer Clock is slow then the interrupt handler is maybe
started and reacts
on an previous captured data.
* Workaround: none.
* Modification: CCRIFGx is set when the timer data is captured. |
TA6
top |
CAP = 1: Capture event recognized at -TimerClock and cleared at +TimerClock.
* Description: The capture event is internally latched and will be
only reset
with the next positve edge of Timer Clock if the according
interrupt flag CCIFG is set.
Example which works correct,
CCIFGx is set min. one Timer Clock
| |
.... v.... v.... .... .
Timer Clock ..../ \..../ \..../ \..../ \..../
Capture Event, . : :
ext. applied ....../ \.....:.........:.....................
Capture Event, .......:.........:
int. latched ....../ : \.....................
Interrupt Flag :.............
CCIFGx ............../ : \.................
Reset Capture :...
Event Latch ......................../ \.................
Example which works not correct,
CCIFGx is set less than one Timer Clock
| |
.... v.... v.... .... .
Timer Clock ..../ \..../ \..../ \..../ \..../
Capture Event, . : :
ext. applied ....../ \.....:.........:.....................
Capture Event, .......:...............................
int. latched ....../ : :
Interrupt Flag :...... :
CCIFGx ............../ \..:.....................
Reset Capture : :
Event Latch ..............................................
No reset of capture event latch possible: permanent capture!
* Workaround: none. * Modification: The capture event latch is reset when
the interrupt flag is set or compare mode is selected. |
TA7
top |
Special Cases described in the Architecture Guide and Module Library
1996
(SLAUE10B) page 11-39 and section 11.4.2 are not valid. After the timer
was released from Halt, the timer continues to operate with the next +Timer
Clock. |
TA8
top |
Additional informations on PWM output unit OUx
The 16-bit Timer TAR is incremented at +TimerClock
Prior to this the EQUx is already there at -TimerClock
| | | |
....v v....v v.... .... .
Timer Clock ..../ \..../ \..../ \..../ \..../
.... ......... ......... ......... ......... .
TAR ....X.........XTAR=EQUx.X....X....X.........X.
.........
EQUx ........./ \..........................
.........
EQU0, delayed .................../ \................
EQU0 delayed is used in UP Mode, not EQU0!
The Mode is defined by the bits OM2, OM1 and OM0. The Outx signal is
changed with the +TimerClock (D -> Outx signal)
Mode1 Mode5
EQU0 EQUx D D
x 0 Outx (no change) Outx
x 1 1 (set) 0 (reset)
Mode2 Mode6
EQU0 EQUx D D
0 0 Outx (no change) Outx (no change)
0 1 !Outx (toggle) !Outx (toggle)
1 0 0 (reset) 1 (set)
1 1 1 0
Mode3 Mode7
EQU0 EQUx D D
0 0 Outx (no change) Outx (no change)
0 1 1 (set) 0 (reset)
1 0 0 (reset) 1 (set)
1 1 1 0
Mode4
EQU0 EQUx D
x 0 Outx (no change)
x 1 !Outx (toggle)
|
| TA9 |
Select direction of P3.x/TAx, see P2 |
TA10
top |
PWM output unit OUx, Puls width in UP/DOWN Mode if CCRx=0
* Description: The PWM output unit toggles if CCRx = 0 and UP/DOWN
mode and
Toggle/Reset or Toggle/Set mode is selected.
* Workaround: Test by software if CCRx should be loaded with 0 and
keep the Out signal
to low or high via e.g Set or Reset mode of the Output Unit
or via Port function.
* Modification: Toggling is disabled if CCRx = 0 with following conditions:
UP/DOWN .and. Toggle/Reset .and. EQUx .and. (TAR=0) ==> OUTx
= 0.
UP/DOWN .and. Toggle/Set .and. EQUx .and.
(TAR=0) ==> OUTx = 1. |
US1
top |
UART Mode:
Modulation of transmitted stop bit. Valid if one stop bit is used (SP=0
in UCTL)
* Description: Modulation of bit timing for stop bit during transmission
(UART
mode) always depends on the LSB of the Modulation
control register m0 and
not on the responsible modulation bit.
* Workaround: none.
* Modification: the responsible modulation bit in the modulation control
register is used. |
US2
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UART Mode: Transmit enable UTXE (Arch. Guide 12-11, 1996)
* Description: If the bit UTXE is reset only the transmission of the
character
in the transmit shift register will be completed. The
data in the transmit
buffer already there or written to will not be transmitted.
* Workaround: The software can check the transmit empty bit TXEPT
before the UTXE bit is reset.
* Modification: All characters written to the transmitter buffer -
before
UTXE was reset - will be transmitted. |
US3
top |
SPI, Slave Mode: Control bit TXEPT (Arch. Guide 13-13, 1996):
* Description: Control bit TXEPT (Transmitter empty) is not set if
SPI slave mode
is selected and the transmit shift register is empty.
In the SPI slave mode
the receiver (slave) is controlled only by received data,
depending on the number
of external shift clocks at UCLK (often also SCLK called).
* Workaround: Use receive interrupt flag URXIFG to get information
that a character
is completely received/transmitted.
* Modification: none. |
US4
top |
SPI, Master Mode: Transmit enable bit UTXE (Arch. Guide 13-7,
1996):
* Description: If the bit UTXE is reset the actual transmission of
the character will be
completed. Any further write to the transmit buffer deliveres
the SPI clock at the
UCLK pin, but no data is transmitted. The level at SIMO
signal is equal to the
latest bit transmitted.
* Workaround: Software should not write to UTXBUF if UTXE bit is reset.
To stop
receive in the master mode the bits UTXE and URXE must
be reset or set within
one instruction (bis.b #(UTXE+URXE),&ME2).
* Modification: Only one control bit is used to enable/disable the
SPI operation. The
enable bit is called USPIE and is located in the special
function register ME2.0;
address 05h, 0. The bit ME2.1 of no relevance.
* SPI Master Mode: All characters written to the transmit buffer UTXBUF,
before USPIE is reset, are transmitted - not only the
actual tranmitted character.
* SPI Slave Mode: This is the receive mode and therefore only the current
receive
operation is completed. Characters in the transmit buffer
UTXBUF are not transmitted |
US5
top |
SPI, Master Mode: Enable receiver with bit URXE, feedback to
URXIFG
* Description: Switching on the receiver (URXE=1) can set the receive
interrupt
flag URXIFG (if SWRST=0).
* Workaround: Enable (or disable) of transmit and receive within one
instruction
(bis.b #URXE+UTXE,&ME2) and when software reset is
active.
* Modification: Only one bit enables/disables the
SPI: USPIE. |
US6
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SPI, Slave Mode: Enable receiver with bit URXE, feedback to
URXIFG
* Description: Switching on the receiver during the active SPI clock
phase (level at
UCLK depends on CKPH and CKPL) results in an immediately
receive interrupt
with the next SPI clock phase. Switching on the receiver
asynchronously to a data
transmission can cause anyway problems.
* Workaround: Proper synchronization methods must be used in such applications.
* Modification: Asynchronous enable of the SPI must be solved only
by the
application hardware/protocol itself. * Definition of
'Start' signal: Start = SWRST .or. .not.(USPIE)
_
CKPL CKPH
.. .. .. .. .. .. .. .. .. .. ..
0 0 UCLK ..../ \../ \../ \../ \../ \../ \../ \../ \../ \../ \../ \..
: : : : : : : : : : :
.... .. .. :.. .. .. .. .. .. .. .. ..
1 0 UCLK \../ \../ \../ \../ \../ \../ \../ \../ \../ \../ \../
: : : : : : : : : : :
............ : : : : : : : : : :
'Start' \\\\\.........................................................
Shift : : : : : : : : : :
DataIn.............I.....I.....I.....I.....I.....I.....I.....I.....I.....I..
Shift 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
DataOut...XXXXXXXXX...I.....I.....I.....I.....I.....I.....I.....I.....I.....
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
: ....................
URXIFG................................................./...../
........... ........................................................
UTXIFG XX/
The interrupt flag URXIFG is set with the 7th (CHAR=0) or 8th (CHAR=1)
edge of the UCLK signal. In the asynchronous start situation this characters
are collected asynchronous to the frame - the first collected bit
must not be the first bit of the character applied to SIMO!
The interrupt flag UTXIFG is set with the first edge (1.) of the
UCLK signal. In the asynchronous start situation this characters are
transmitted asynchronous to the frame - the first bit sent must
must not be the first bit of the character collected by the receiver!
CKPL CKPH
.. .. .. .. .. .. .. .. .. .. .
0 1 UCLK ..../ \../ \../ \../ \../ \../ \../ \../ \../ \../ \../
: : : : : : : : : :
.... .. .. :.. .. .. .. .. .. .. ..
1 1 UCLK \../ \../ \../ \../ \../ \../ \../ \../ \../ \../ \.
: : : : : : : : : :
.......... .. : : : : : : : : :
'Start' \\\.\\....................................................
Shift a b : : : : : : : :
DataIn..........I.....I.....I.....I.....I.....I.....I.....I.....I.....I.
Shift 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
DataOutXXXX . .....I.....I.....I.....I.....I.....I.....I.....I.....I....
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
: : ...................
a:URXIFG............................................../...../
......... ......................... . . . . . . . . .............
a:UTXIFG.........X///. . . . . . . . . . . ................./...../
: : 7 or 8 bits/char.
: .........................
b:URXIFG......................................../...../
.......... . . . . . . . . . . . . . . . . . . ...................
b:UTXIFG......../ . . . . . . . . . . . . . . . . . . /...../
: 7 or 8 bits/char.
Note: 'Start' during time 'a': UTXIFG is set with the first +edge (CKPL=0)
or -edge (CKPL=1) of UCLK
'Start' during time 'b': UTXIFG is set with the 7th/8th +edge (CKPL=0)
or -edge (CKPL=1) of UCLK
If it is the 7th or 8th depend on the selected length of a character
It is defined by the CHAR bit in the control regiter UCTL.
UTXIFG, SWRST: during SWRST is set the UTXIFG is set
UTXIFG, time 'b': if SWRST=0 then UTXIFG is set when USPIE changes
from reset to set (SPI is enabled).
|
US7
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UART Mode: Baud rate generator, transmit and receive
* Description: The receive/transmit baudrate generators are only switched
of
if the receiver/transmitter is disabled (URXE=0/UTXE=0)
or if software reset
SWRST is set.
* Workaround: none.
* Modification:
The transmit baudrate generator is always switched
off if all data, written
to the transmit buffer UTXBUF before UTXE is reset, are
transmittted.
The receive baudrate generator is always switched
off if the receipt is completed.
The receive baud rate generator is switch off also if
a break condition
was detected but is restarted when the break condition
is removed
(space_to_mark transition). The generator runs for 10
bit periods to
detect idle condition. The next start condition - mark_to_space
transition -
restarts colection the next character. |
US8
top |
UART or SPI Master Mode: Sequence write to UTXBUF and disable
transmitter
Bit TXEPT is reset. The sequence 'write to UTXBUF' and
disable transmitter
(UTXE=0) can result in an transmission of the character
or no transmission. It depends
if there is a negative edge of the transmit clock BITCLK
between this to actions. If the
transmission is not started then it happens immediately
if the transmitter is enabled again.
* Workaround: Check for TXEPT=1 or UTXIFG=1 before transmitter is disabled.
* Modification: Each character which is written to the transmit buffer
before the transmitter
is disabled will be transmitted. No workaround is needed
anymore. |
US9
top |
UART or SPI Master Mode: Sequence write to UTXBUF and disable
transmitter
Bit TXEPT is reset. With the sequence 'write to UTXBUF'
and disable transmitter
(UTXE=0) the character will not be transmitted. The transmission
is started immediately
if the transmitter is enabled again.
* Workaround: Check for TXEPT=1 or UTXIFG=1 before transmitter is disabled.
* Modification: Each character which is written to the transmit buffer
before the transmitter
is disabled will be transmitted. No workaround is needed
anymore. |
US10
top |
UART Mode: Set of URXIFG when break is detected
The receive interrupt flag is not set when a break is
detected.
* Workaround: none.
* Modification: The receive interrupt flag URXIFG is set when break
is detected. |
US11
top |
SPI Mode: Information on the direction control signal from USART
module
* Description: The USART module delivers a direction control signal.
The direction
control signal is used when the USART module input and
output signals are
shared with other pins, e.g. port pins. It drives then
active the direction
of the pin - i/p or o/p - when it is selected by the function
control signal.
* Direction control for SIMO and UCLK signal/pin,
SIMODIR = 0 means input direction
SIMODIR = SYNC .and. MM .and. (STC .or.
STE)
Output direction is selected when SPI + Master Mode is
selected. When 4-pin
SPI is selected (STC=0) input direction is forced by a
low on external STE pin.
* Direction control for SOMI signal/pin, SOMIDIR = 0 means input direction
SOMIDIR = [SYNC .and. .not.(MM)] .or.
[STC .or. .not. (STE)]
Output direction is selected when SPI + Slave Mode is
selected. When 4-pin
SPI is selected (STC=0) input direction is forced by a
low on external STE pin. |
