HOUSTON, TEXAS (May 22, 1995) -- Texas Instruments has expanded its range of digital signal processing solutions for embedded data-and telecommunications applications with the announcement of a new peripheral-rich digital signal processor (DSP).
The new DSP solution, TI's TMS320C57S, is a lower-cost version of TI's TMS320LC57 DSP, announced last year, and is optimized for embedded applications such as mobile radios, navigational communications systems, cellular base stations, and networking equipment including telephony switches, routers, wireless local loop infrastructure systems, and links to ATM, Ethernet, and T1 lines.
Integrating a high-performance 'C5x-series DSP central processing unit (CPU) with 7K Words of on-chip RAM, a zero-overhead buffered serial port (BSP), and a glueless host-port interface (HPI), the 'C57 facilitates the large amounts of data input/output (I/O) required for communications applications while minimizing the load these I/O tasks place on the DSP CPU.
"While the 'C57S can operate at up to 40 MIPS, the power of this performance is made even more significant by the capabilities of the on-chip intelligent peripherals," said TI fixed-point DSP applications manager, Jim Larimer.
With its own dedicated on-chip memory bus, the full-duplex, 40 Mbits/second BSP improves system performance by eliminating the need for the DSP CPU to service real-time data-frame interrupts from system I/O peripherals, such as CODECs or analog-to-digital (A/D) converters. Similarly, the independent 8-bit HPI requires no DSP CPU loading, providing a direct interface between the 'C57S and standard host microprocessors or other DSPs. Both peripherals are fully functional even when the 'C57S is in idle or reset mode, dramatically reducing system power consumption.
The combined processing and peripheral features of the 'C57S make it an ideal data I/O engine for any DSP application that requires high-speed serial transmission, host-processor communication, large amounts of on-chip code and/or data, plus low power and high-performance.
The 'C57S introduces four differences from TI's 'LC57. The 'C57S features:
Various boot-loader modes allow the 'C57S to boot from an 8-bit EPROM, the chip's standard serial port, or the HPI for a high degree of system-design flexibility.
TI's newest digital signal processing solution is packaged in a 144-pin TQFP with a .5 mm pitch. It is provided in 40 MHz (20 MIPS), 57 MHz (28.5 MIPS), and 80 MHz (40 MIPS) versions.
The 'C57S is scheduled for sampling early in the third quarter of 1995 and is expected to ship at full production levels late in the fourth quarter. Planned pricing for the 40 MHz version is $24.25 each in 10,000 unit quantities.
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