Technical Fact Sheet

TMS320C545 and TMS320C546 Digital Signal Processors

TMS320C545 and TMS320C546 digital signal processors have the core architecture, large memory, and intelligent peripherals to enable next generation wireless communication s systems that require half-rate, enhanced full rate, and enhanced variable rate voice coding.

Features	Benefits
Integrated Viterbi accelerator	Reduces Viterbi butterfly update
(compare select store unit)	down to only four instruction
	cycles for GSM channel decoding.
Host Port Interface	Glueless interface to standard 8-bit
(‘C545 only)	processors & other TMS320 DSPs.
	Up to 2K words of shared memory
	is accessible by host processor & DSP.
Auto Buffered Serial Port	2K word data buffer that reduces processor
	overhead. Buffered data can be read into
	RAM in only one instruction cycle.
Large On-chip Memory	Ability to adapt to changing standards &
(‘C545-6Kx16 words RAM;	add more features. Fewer components per system.
48Kx16 words ROM)
(‘C546-6Kx16 words RAM;
48Kx16 words ROM)
Four internal buses and dual	Enables multiple operand operations
address generators	and reduces memory bottlenecks.
40-bit adder and two 40-bit	Supports crucial parallel operations
accumulators	such as read & store, or add &
	subtract, etc., in one instruction cycle.
Single-cycle normalization	Supports efficient floating-point arithmetic
and single-cycle	useful in vocoding.
exponential encoding
16-bit signed or 17-bit	Provides for efficient implementation of
unsigned multiplication,	voice coders & other DSP applications.
with rounding and saturation
control --- all in one instruction cycle
New single cycle instructions	Executes common DSP tasks efficiently
40-bit arithmetic logic unit	Enables dual one-cycle operations
(ALU) featuring a dual	and supports Viterbi accelerators.
16-bit configuration capability
8 auxiliary registers and	TI’s most advanced fixed-point DSP
software stack	C compiler.

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