DALLAS (December 4, 1995) -- A new high-performance family of gate arrays based on low-power 0.35-micron CMOS technology was announced today by Texas Instruments. The new product offers high speed and low power consumption, making it well suited to the needs of telecommunications, networking and engineering workstation systems designers.
Designated the TGC4000/TEC4000 Series of gate arrays, the family offers both gate array and embedded array options with quad-level metalization and up to 1.7 million gates. The TGC4000 Series achieves an increase of 42 percent in density and 20 percent in speed over TI's enhanced 0.44-micron TGC3000T Series, itself one of the fastest sub-0.5-micron application-specific integrated circuit (ASIC) products in the industry. An improved base cell architecture, together with redesigned higher-level functions, compress the circuitry of designs on the arrays to further maximize density and minimize delays and power, especially in critical paths. Optimized for 3.3V designs, its power dissipation rating of only 0.37 uW/MHz/gate makes the TGC4000 Series one of the lowest-power ASIC CMOS technologies available in the market.
"The TGC4000 gate array family is based on TI's proven 0.35-micron manufacturing process," said Mohan Maheswaran, Worldwide ASIC Strategic Marketing Manager. "We know how to get the greatest density, highest performance and lowest power out of our processes. So the TGC4000 Series, like other TI ASIC products, brings leading-edge capabilities to TI customers."
A variety of features make the new product appropriate for its targeted high-performance applications. Enhanced high-speed I/O cells and multiplexer/demultiplexer modules capable of speeds up to 850MHz, combined with the high performance ball grid array (BGA) packages, have been developed specifically for high speed ATM (Asynchronous Transfer Mode) and SDH applications in close cooperation with leading end equipment manufacturers. Macros for complex functions such as phase aligners and analog and digital phase-locked loops help shorten design cycles and speed time to market. Multiport wide-bit-width memories and fast memories running at speeds up to 170 MHz provide design flexibility for numerous high-performance applications. TGC4000 rounds out a robust set of special features with a variety of I/O options including CML, HSTL, DPECL, Universal PCI, LVDS and TTL/LVCMOS.
TGC4000 gate arrays are accompanied by a complete suite of CAD capabilities in the TI Design Support Software environment. This suite integrates a wide variety of the most popular and most advanced third-party tools for maximum design freedom, including tools from Synopsys, Cadence, Mentor Graphics and IKOS. Design cycle time is reduced with friendly capabilities such as clock tree synthesis, hierarchical layout and a macro library optimized for logic synthesis. Power estimation tools are included which allow the designer to maximize the benefits of the low power architecture of the TGC4000 family early in the design cycle.
"The TGC4000 series is a customer-driven product," said Maheswaran. "We have worked closely with customers to put the features into the product that are most needed by high-performance applications such as telecom switches and workstations."
TI will begin accepting designs for TGC4000/TEC4000 Series arrays early in 1996.
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