TMS626162 16-Megabit Synchronous DRAM Fact Sheet

Summary of Key Features:

• 16 Megabits organized in 512K words by 16 bits wide by two banks

• Synchronized to system clock for simplified design and enhanced performance over traditional asynchronous DRAM

• Pipeline architecture allows a new column address entry on every single clock cycle

• High bandwidth up to 83 MHz

• High speed allows for a Unified Memory Architecture (UMA) with no separate graphics memory and elimination of discrete cache in cost sensitive applications

Programmable for serial or interleaved output

• Programmable burst lengths of one, two, four, or eight words, or a full page

• Available in industry standard 168-pin DIMMs (Dual Inline Memory Modules)

• IBIS I/O interface models available for system design

• High-speed, low noise LVTTL interface

• Compatible with JEDEC memory standards

• Power-down mode to conserve power consumption

• Fabricated using the state-of-the-art EPIC (Enhanced Performance Implanted CMOS)

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Trademarks:

EPIC is a trademark of Texas Instruments Incorporated.

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