HOUSTON (Feb. 12, 1996) -- Strengthening its leadership in performance for fixed-point digital signal processors (DSPs), Texas Instruments today announced plans to achieve 100 million instructions per second (MIPS) in late 1996 on a 16-bit, fixed-point DSP. Placing a milestone product along the TI DSP solutions roadmap, the company also disclosed development of a new low-voltage, 16-bit, fixed-point DSP with large on-chip static RAM to be introduced initially at 66 MIPS and subsequently offered at 100 MIPS.
"TI is redefining the DSP landscape," said Mike Hames, Vice President, Semiconductor Group and Worldwide DSP Manager. "TI plans to reach 100 MIPS performance first. The critical steps to do this include using a .25 micron quad-level metal process technology, a streamlined architecture and increased clock speeds."
At 100 MIPS, it becomes possible for systems to perform a variety of processing functions on a single chip that today have to be distributed. For example, within a digital cellular basestation, multiple full-duplex channels of vocoding and echo cancellation can be handled by a 100 MIPS TMS320C54x DSP, minimizing system cost, space and power. Another possibility is the integration of the following multimedia and telephony tasks onto a single 100 MIPS 'C54x DSP: V.34, digital simultaneous voice data (DSVD), full-duplex speakerphone, FM and wavetable synthesis, 3-D sound, and a variety of telephony algorithms.
The 16-bit, fixed-point DSP announced today, the TMS320LC548, increases the available performance of large on-chip RAM DSPs with initial introduction at 66 MIPS and plans to migrate to 100 MIPS. It combines high-performance with low system power consumption, making it useful in a variety of low-power, portable systems that can be brought to market quickly. Typical applications include digital cellular base stations, wired and wireless telephones, mobile radios, personal digital assistants (PDAs), and high-end applications that merge digital telecommunications and networking, such as private branch exchanges (PBXs), T1/E1 line cards, and other multimedia and telephony systems with high-speed modem or Integrated Services Digital Networks (ISDN) capabilities.
"To develop the new 'LC548, we've leveraged our expertise in developing high-performance, low-power ICs for wireless telephones," said Jim Larimer, TI DSP fixed-point applications manager. "The same product strengths and technology that made other DSPs in the 'C54x family ideal for the mobility and high processing requirements of wireless phones is used in the 'LC548 to support a wider variety of applications."
With the 'LC548's high level of integration, designers will be able to bring software functions from multiple DSPs together into a single chip. The 32K words of fast, static random-access memory (SRAM) integrated with the 'LC548 are essential to reconfigurable systems that must frequently swap software code in order to handle different tasks. For example, a cellular base station may need to reload software for dealing with a variety of calls using different cellular standards. Other applications that can benefit include systems that require zero-wait state memory accesses to code or data on-chip, and PC Cards and other systems with rigid space constraints that preclude additional memory devices.
Supporting the large on-chip SRAM is the capability to address up to 8M words of code. With such a large address space, the 'LC548 can reconfigure itself in operation to run a wide variety of software algorithms available to it off-chip, using an enormous external memory pool.
Integrated peripherals include two high-speed buffered serial ports, one time-division multiplexed serial port, a host port interface and a timer. By being on-chip, these functions speed up signal transfer and also serve to simplify design, helping equipment manufacturers develop their products and bring them to market faster. In addition, both buffered serial ports and the host port interface have separate dedicated buses to the on-chip memory that allows data transfers even while the CPU is in IDLE mode.
Architectural features maximize the efficiency of C programming, which can be used in conjunction with the Code Composer™ Windows®-based programming environment to simplify software development. Algebraic and mnemonic assemblers also make code development easier. A pin-compatible DSP of the same TMS320 family, the 'LC542, is available now and can be used to initiate 'LC548 designs.
One version of the 'C548 will operate at 3.3 volts with 66 MIPS performance ('LC548), another at 3.0 volts with 60 MIPS performance ('VC548). These combinations of low voltages and high performance ratings are well suited for wireless telecommunications and other mobile systems that need to perform complex functions and at the same time conserve battery power.
"The 'LC548 will offer twice the performance of the nearest competitive fixed-point DSP, opening up new possibilities in high-performance applications," said Ron Wages, TI's marketing manager for DSP products. "With its enhancements in manufacturing process, architecture and functional integration, the 'C548 shows how we plan to achieve 100 MIPS for 16-bit fixed-point digital signal processing within a year."
Sampling of the 66 MIPS version of the 'LC548 DSP is planned for early 3Q96, with volume production planned for 4Q96. The device will be packaged in a 144-pin thin quad flatpack (TQFP) and will be available from TI and TI Authorized Distributors worldwide.
# # #
Trademarks:
Windows is a registered trademark of Microsoft Corporation.
Code Composer is a trademark of GO DSP.
Reader Inquiry: 1-800-477-8924, ext. 5300
Please refer to Profile #SPR191
Search the Semiconductor News Release Archives
TI Home
Search
Semiconductor Home