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DALLAS (July 15, 1996) -- A new flexible, cost-effective chipset for optimum connection between either Ethernet or Token Ring local area networks (LANs) to asynchronous transfer mode (ATM) networks was announced today by Texas Instruments. Dubbed HyperSAR+, the chipset incorporates a high performance segmentation and reassembly (SAR), with a traffic management scheduler.
The HyperSAR+ chipset is designed to simplify the original equipment manufacturer's (OEM's) product development cycle by providing a two chip solution and all the necessary software to implement ABR traffic management. The chipset provides the flexibility to add ABR functionality as needed. The HyperSAR+ chipset can be combined with the TNETA1500 ATM physical layer interface device to provide a complete 155 Mbps ATM uplink capability.
With added performance features, the HyperSAR+ high-performance SAR is backwards pinout compatible with ThunderCELL's™ HyperSAR™ (TNETA1570). It is ideal for applications that require simultaneous, efficient transport of bursty data along with constant bit rate (CBR) video and audio. The device provides support for the full ATM address range(VPI/VCI values) required for virtual LANs. The fully defined scheduler interface on the SAR allows OEMs to provide a differentiated solution. In addition, the SAR eliminates the need for a large off-chip SRAM through intelligent, efficient algorithms for channel allocation.
The HyperSAR+ traffic management scheduler enables an ABR implementation that supports up to 2,048 simultaneously active ABR channels, facilitating LAN emulation. The traffic management scheduler is a software downloadable device with a well defined interface to the HyperSAR+. Housing the traffic management scheduler on a separate chip enables designers to track the ABR specification and incorporate modifications by downloading updated code to the scheduler, rather than changing hardware designs. The HyperSAR+ chipset conforms to the ATM Forum Traffic Management 4.0 specification and the ITU-T I-371 Recommendation (formally called the CCITT).
As the latest addition to TI's ThunderCELL family of ATM silicon products, the HyperSAR+ chipset further drives ATM into mainstream networks. "The HyperSAR+ chipset enhances our commitment to the ongoing evolution of ATM network products," said Gregory Waters, Director of Marketing for the Networking Business Unit. "The HyperSAR+ chipset not only provides a traffic management solution for ATM networks now, but also enables a high performance connection between Ethernet and ATM networks. Due to the built-in flexibility that is inherent in the HyperSAR+ architecture, we can also provide our customers a variety of choice to implement an ABR traffic management scheme as needed.
"TI's HyperSAR+ chipset enables 3Com Premises Distribution Division (PDD) to provide our customers with a cost effective, high-performance ATM solution. It gives us the flexibility to achieve transparent introduction of ABR traffic management now or in the future" said Mark Wingrove, 3Com PDD's ATM Programme Manager. "HyperSAR+ complements our own ASIC technology in the SuperStack LinkSwitch 1000 ATM module. We can offer customers the ability to realize a high-performance connection between their installed Ethernet LANs and high-speed ATM backbones."
Planned packaging for the HyperSAR+ Traffic Management chipset is a 240 pin MQUAD flat pack for the HyperSAR+ and a 176 pin thin plastic quad flat pack (TQFP) for the traffic management scheduler. HyperSAR+ samples and prototypes will be available to customers in August. The traffic management scheduler will be available 4Q 1996. The chipset is priced at $120 in quantity of 1000.
Trademarks:
HyperSAR, HyperSAR+ and ThunderCELL are trademarks of Texas Instruments
Incorporated.
Reader Inquiry: 1-800-477-8924, ext. 5300
Please refer to Literature # SDNT009
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