TSC6000 Series 0.18um CMOS Standard Cell Family

• 0.18um(Leff)/0.21um (Drawn) CMOS process
• Up to 6 levels of metal
• Up to 30-million equivalent logic gates (16 million available gates)
• Ultra-low power dissipation rated at 0.025uW/MHz/gate (@1.8V)
• Sub-l volt core and I/O options
• Digital phase-lock-loops
• Analog macro library (8/10-bit Video A/D, 8/10-bit Video DAC, 8/10-bit SAR A/D, phase-lock-loop, RF clock squarer)
• I/O
  • 3.3V and 2.5V interface capabilities
  • TTL/LVCMOS, SCSI, ATA, 1394
• Cores
  • DSP, ARM, microprocessor, MPEG, ATM, PHY, MAC, PCI
• Memory
  Optimized for area and low-power
  SRAM, FLASH, ROM, Datapath
• Packaging

TQFP, PQFP

• CAD
  Cadence, Synopsys, Mentor, IKOS and Viewlogic tool support
  TI SubChip module reuse flow
  Power management methodologies (clock tree synthesis, power synthesis)
  Hierarchical design flow methodologies
  Hardware and software co-design environment
  

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