The TLC320AD56 optimizes TI’s world leadership in digital signal processing solutions. The newest member of the family has a glueless interface, via serial port, to the TMS320 family of digital signal processors (DSPs) reducing overall system cost and board space.
The TLC320AD56 offers a typical signal to distortion ratio of 103 dB at 3V and 85 at 5V on the ADC channel, and 91 dB on the DAC channel. It also offers a minimum signal-to-noise ratio (SNR) of 86 dB on the ADC channel and 85 dB on the DAC channel. One advantage of 64X oversampling sigma delta conversion is that it requires only a single pole R-C for the anti-aliasing filter significantly further reducing overhead system cost. This is due to the sample frequency being far enough away from the signal frequency band that a single pole achieves adequate rejection. The ’AD56 consists of two serial synchronous conversion paths, one for each data direction, and includes an interpolation filter before the DAC and a decimation filter after the ADC. Other overhead functions include on-chip timing and control. It has a digital loopback function that allows for in-circuit system level tests. This feeds the appropriate output to the corresponding input on the IC. The ’AD56 features a serial port interface whose options include reset, power-down, communications protocol, serial clock rate, and test mode. The power down mode reduces the power dissipation from the typical operating level of 100 mW to only 2.5 mW.
The TLC320AD56 is available in the 28 pin PLCC (plastic lead chip carrier) package and the 48 pin TQFP (quad flat pack) package, and will be available in the 28 pin SOIC package.
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