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Chipset Breaks Internet Bandwidth BarrierAvailable Bit Rate Scheduler Enables Quality of Service
DALLAS (March 24, 1997) -- Texas Instruments (TI) announces availability of production quantities of the HyperSAR+ segmentation and reassembly (SAR) and traffic management chipset for asynchronous transfer mode (ATM). The traffic management scheduler offers original equipment manufacturers (OEMs) and Internet service providers (ISPs) an important tool in eliminating network bottlenecks through a cost-effective bandwidth management solution. The TNETA1585 traffic management scheduler implements the ATM Forum's available bit rate (ABR) specification for an efficient, flexible solution to creating service levels on the Internet and in other network environments. ISPs will use quality of service (QoS) to adjust fees and traffic according to customer requirements. For example, customers requiring high-priority, real-time data will purchase constant bit rate (CBR) bandwidth. Lower fees will apply for less time-sensitive data on variable bit rate (VBR) and for non-time-sensitive service on ABR. TI's scheduler enables these service categories in a fair, robust solution. Fair ABR Scheduling Maximizes Quality of Service CapabilitiesThe '1585 manages cell traffic with high-performance scheduling algorithms. These algorithms are critical to avoid network flooding and to assign bandwidth fairly for all connections. Unlike bucket sort (or "calendar") schedulers, the '1585's dynamic priority queue meets the ATM Forums Traffic Management 4.0 Max-Min Fair Share criteria by providing equal bandwidth between all connections. Algorithm efficiency also allows the scheduler to handle resource management (RM) cells in a single cell time, enabling back-to-back RM cells. As a result, floating point fields may appear in any word of any cell without loss. Chipset and Support Offer Clear Benefits for CustomersOEMs select the solution that provides their customers the highest performance at the lowest cost. TI provides customers with what they need through a full range of features:
SAR Chip Complements Scheduler for FlexibilityThe separate traffic management scheduler chip functions in tandem with the TNETA1575 SAR to provide maximum upgradability as customers implement the committee-approved ABR standard in real-world networks. As the latest member of TI's family of SAR solutions, the chip houses established SAR functions that have been proven in working systems. As designers pursue QoS, designs with the '1575 add ABR while maintaining their SAR investment. As the committee-approved standard moves into real-world networks, TI's scheduler software upgradability completes the flexible solution. This need was illustrated by the Traffic Management ABR Addendum approved in January, 1997. TI's Commitment to Timely SolutionsTI has participated in the ATM Forum's Traffic Management Work Group since September 1994 and has been actively involved in ABR research and implementation. As a result of this commitment and involvement, TI began sampling the HyperSAR+ two-chip chipset solution in August 1996, just four months after the ATM Forum set the ABR specification. The chipset is currently available in production level quantities at $120 per thousand.
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