TI Discloses World's Highest Performing Floating-Point DSP Core
TI to Sample 1 GFLOPS Floating-Point DSP
in 1998
HOUSTON (Oct. 13, 1997) -- Raising the bar yet again on DSP performance, Texas Instruments (TI) (NYSE: TXN) disclosed today the world's most powerful floating-point digital signal processor (DSP) CPU core with up to 10 times that of today's floating-point performance at 1 billion floating-point operations per second (GFLOPS). That performance will enable next-generation advanced applications and bring faster speed, precision and dynamic range to applications including wireless local loop base stations, beam-forming base stations, virtual reality 3-D graphics, voice mail, speech recognition, audio, radar, industrial control, atmospheric modeling, finite element analysis and imaging such as fingerprint recognition, ultrasound and MRI.
"TI is the first DSP solutions provider to offer a code-compatible fixed- and floating-point architecture with a single learning curve," said Ray Simar, TI Fellow and chief architect speaking from Microprocessor Forum in San Jose. "The VelociTI™ architecture will allow developers to start with floating-point design and easily migrate their design to more cost efficient fixed-point solutions."
The new CPU core will support a new 32-bit, floating-point line of DSPs, the TMS320C67x generation, which complements and extends the groundbreaking advanced Very-Long Instruction Word (VLIW) VelociTI architecture already in use in TI's industry-leading TMS320C62x fixed-point DSPs. The 'C67x floating-point core can achieve 1 GFLOPS at 167 MHz today, and TI plans to triple 'C67x performance to 3 GFLOPS by the end of the decade. This performance will drastically reduce system chip count from as many as 10 DSP chips down to one 'C67x.
Because the 'C67x instruction set is a superset of the 'C62x, designers can use existing 'C6x tools to begin development of 'C67x floating-point systems today. In 1Q98, TI plans to release a 'C6x tools set that will fully support floating-point instructions. This compatibility allows customers to meet time-to-market goals on advanced, next-generation floating-point applications.
As the world's leading DSP solutions provider, TI also has the largest number of floating-point customers worldwide and continues to encourage new designs using the 32-bit, floating-point TMS320C3x and TMS320C4x generations. For customers who need more performance, TI plans to offer translation tools from these existing architectures to the new 'C67x generation that will minimize rework and maximize 'C3x and 'C4x code investment. This 'C67x roadmap extends TI's DSP market leadership well into the next century.
"The 'C67x technology will enable 10 times the performance at today's floating-point prices," said Mike Hames, TI Semiconductor Group vice president and worldwide DSP manager. "We plan to offer a broad 'C67x floating-point product offering. Performance will range from 1 GFLOPS up to 3 GFLOPS by the year 2000. This technology will also enable prices less than $50 per device. In addition, TI will offer supporting analog-to-digital data converter products for future 'C67x devices."
Leading DSP third party companies who will support the new 'C67x core include 3L, Ariel Corporation, Coreco, Inc., DNA Enterprises, Inc., DSP Research, Inc., DSP Software Engineering, Inc., Eonic Systems, GO DSP Corporation, Hunt Engineering, Loughborough Sound Images (LSI), Mizar, Inc., Pentek, Inc., RadiSys Corporation, Spectron, Spectrum Signal Processing, Sundance Multiprocessor Technology, Ltd., Transtech Parallel Systems Corporation, and White Mountain DSP, Inc.
Sampling of the first 'C67x devices, manufactured in TI's 0.18-micron TImeline™ technology, is planned for the second half of 1998. For more information, visit the TI 'C67x world wide web address: 
http://www.ti.com/sc/c67x.
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