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TMS320C27x Architecture Feature Summary

TI's Groundbreaking TMS320C27x Architecture Balances the Best Features of DSPs and MCUs

New TMS320C27x Architecture Unites the Best Features of DSPs and Microcontrollers for Real-Time Embedded Systems

TI's TMS320C27x Architecture Redefines DSP for the Storage World, Enabling Future-Ready System-on-a-Chip Development for Mass Storage Electronics

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TI's Groundbreaking TMS320C27x Architecture Balances the Best Features of DSPs and MCUs

Texas Instruments’ (TI) new TMS320C27x DSP architecture combines the high-speed multiply-and-accumulate (MAC) operations of digital signal processors (DSPs) with the intensive input/output (I/O) operations characteristic of microcontrollers (MCUs). The result is that this one DSP can provide the high-speed number crunching needed for real-time signal processing, together with the fast context switch and data manipulation capabilities required for control tasks – eliminating the need for a MCU altogether.

• High performance. The 'C27x's DSP architecture and instructions are optimized for the heavily-used signal-processing operations of a system. As a result, the 'C27x far outperforms MCUs in real-time tasks with up to 100 million instructions per second (MIPS).

• Compact code. The 'C27x offers MCU-like code density for control operations, so that less program memory is required, or more tasks can be performed using the same amount of memory. More compact code also executes faster and promotes reliability by protecting operations from interrupts.
  • As an example, a single instruction directs the processor to read data from memory, modify it and write it back. Virtually all DSPs, and even RISC-based MCUs, require two, or even three, steps to perform this I/O operation, which is commonly used in embedded systems.

• Fast learning curve. The 'C27x instruction set is more consistent with the model MCU programmers are accustomed to using, helping to minimize learning and development times.

• Fast interrupt response. 'C27x interrupt latency is 80 ns. A fully-automatic context switch is performed in 160 ns, an order of magnitude less than that of popular MCUs.

• Flexible I/O. The 'C27x core bus architecture allows for the customization of signals and timing to application needs. Examples:
  • Devices can be designed to interface directly with any PC peripheral, a feature that supports mass storage systems well.

  • The high-performance architecture can handle the processing protocol required for the 400- and 800-Mbps IEEE 1394 high-speed serial bus standards that are increasingly used for digital consumer products.