Application Reports for DIGITAL LOGIC

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BACKPLANE LOGIC (GTL, FB/FBPLUS, ETL)

1. GTL/BTL: A LOW-SWING SOLUTION FOR HIGH-SPEED DIGITAL LOGIC

scea003a.pdf (198 KBytes) (Abstract)

2. NEXT-GENERATION BTL/FUTUREBUS TRANSCEIVERS ALLOW SINGLE-SIDED SMT MANUFACTURING

scba003c.pdf (66 KBytes) (Abstract)

3. SPARC MBUS-TO-FUTUREBUSPLUS BRIDGE USING THE TI FUTUREBUSPLUS CHIPSET

scaa019a.pdf (66 KBytes) (Abstract)

BOUNDARY SCAN (JTAG) BUS DEVICES

1. A LOOK AT BOUNDARY SCAN FROM A DESIGNER'S PERSPECTIVE

scta028.pdf (154 KBytes) (Abstract)

2. AN IEEE 1149.1 BASED LOGIC/SIGNATURE ANALYZER IN A CHIP

scta034.pdf (1055 KBytes) (Abstract)

3. BOUNDARY SCAN SPEEDS STATIC MEMORY TESTS

scta030.pdf (694 KBytes) (Abstract)

4. DESIGN TRADEOFFS WHEN IMPLEMENTING IEEE 1149.1

scta045a.pdf (79 KBytes) (Abstract)

5. DESIGN-FOR-TEST ANALYSIS OF A BUFFERED SDRAM DUAL-IN-LINE MEMORY MODULE (DIMM)

scta027.pdf (102 KBytes) (Abstract)

6. HARDWARE-BASED EXTENSION TO THE JTAG ARCHITECTURE

scta044.pdf (588 KBytes) (Abstract)

7. HIERARCHICALLY ACCESSING IEEE 1149.1 APPLICATIONS IN A SYSTEM ENVIRONMENT

scta033.pdf (884 KBytes) (Abstract)

8. IEEE 1149.1 USE IN DESIGN FOR VERIFICATION AND TESTABILITY

scta042.pdf (383 KBytes) (Abstract)

9. IMPACT OF JTAG/IEEE 1149.1 TESTABILITY ON RELIABILITY

scta041a.pdf (64 KBytes) (Abstract)

10. JTAG-COMPATIBLE DEVICES SIMPLIFY BOARD LEVEL DESIGN FOR TESTABILITY

scta040.pdf (636 KBytes) (Abstract)

11. JTAG/IEEE 1149.1 DESIGN CONSIDERATIONS

scta029.pdf (132 KBytes) (Abstract)

12. PARTITIONING DESIGNS WITH IEEE 1149.1 SCAN CAPABILITIES

scta031.pdf (478 KBytes) (Abstract)

13. PROPOSED METHOD OF ACCESSING IEEE 1149.1 SERIAL BUSES IN A BACKPLANE ENVIRONMENT

scta032.pdf (1080 KBytes) (Abstract)

14. PROTOTYPE TESTING SIMPLIFIED BY SCANNABLE BUFFERS AND LATCHES

scta039.pdf (675 KBytes) (Abstract)

15. SCAN-BASED DESIGN VERIFICATION- AN ALTERNATIVE APPROACH

scta038.pdf (437 KBytes) (Abstract)

16. SYSTEM TESTABILITY USING STANDARD LOGIC

scta037a.pdf (75 KBytes) (Abstract)

BOUNDARY SCAN (JTAG) SUPPORT DEVICES

1. BUILT-IN SELF-TEST (BIST) USING BOUNDARY SCAN

scta043a.pdf (64 KBytes) (Abstract)

2. WHAT'S AN LFSR?

scta036a.pdf (58 KBytes) (Abstract)

BUS TERMINATION ARRAYS AND NETWORKS

1. IMPLICATIONS OF SLOW OR FLOATING CMOS INPUTS

scba004b.pdf (163 KBytes) (Abstract)

CLOCK DRIVERS/SYNTHESIZERS

1. APPLICATION AND DESIGN CONSIDERATIONS FOR CDC5XX PHASE-LOCK LOOP CLOCK DRIVERS

scaa028.pdf (102 KBytes) (Abstract)

2. CLOCK DISTRIBUTION IN HIGH-PERFORMANCE PCS

scaa030a.pdf (58 KBytes) (Abstract)

3. EMI PREVENTION IN CLOCK-DISTRIBUTION CIRCUITS

scaa031.pdf (93 KBytes) (Abstract)

4. HIGH SPEED CLOCK DISTRIBUTION DESIGN TECHNIQUES FOR CDC 509/516/2509/2510/2516

slma003a.pdf (110 KBytes) (Abstract)

5. MINIMIZING CLOCK DRIVER OUTPUT SKEW USING GANGED OUTPUTS

scaa032.pdf (54 KBytes) (Abstract)

6. PHASE-LOCK LOOP-BASED (PLL) CLOCK DRIVERS: BENEFITS VERSUS COSTS

scaa033a.pdf (52 KBytes) (Abstract)

7. USING CDC2509A/2510A PLL WITH SPREAD SPECTRUM CLOCKING (SSC)

scaa039.pdf (456 KBytes)

D-TYPE (3-STATE) FLIP-FLOPS

1. TIMING DIFFERENCES OF 10-PF VERSUS 50-PF LOADING

scea004.pdf (47 KBytes) (Abstract)

D-TYPE (3-STATE) LATCHES

1. INTERFACING THE TLC5510 ANALOG TO DIGITAL CONVERTER TO THE TMS320C203 DSP

slaa029.pdf (541 KBytes) (Abstract)

DIGITAL LOGIC

1. 12-MM TAPE-AND-REEL COMPONENT-DELIVERY SYSTEM

slza001.pdf (69 KBytes) (Abstract)

2. 3.3-V TO 2.5-V TRANSLATION WITH TEXAS INSTRUMENTS CROSSBAR TECHNOLOGY

scda004a.pdf (32 KBytes)

3. BUS-INTERFACE DEVICES WITH OUTPUT-DAMPING RESISTORS OR REDUCED-DRIVE OUTPUTS

scba012a.pdf (106 KBytes) (Abstract)

4. CMOS POWER CONSUMPTION AND CPD CALCULATION

scaa035b.pdf (91 KBytes) (Abstract)

5. DESIGNING WITH LOGIC

sdya009c.pdf (188 KBytes) (Abstract)

6. FAMILY OF CURVES DEMONSTRATING OUTPUT SKEWS FOR ADVANCED BICMOS DEVICES

scba006a.pdf (81 KBytes) (Abstract)

7. INPUT AND OUTPUT CHARACTERISTICS OF DIGITAL INTEGRATED CIRCUITS

sdya010.pdf (1709 KBytes) (Abstract)

8. K-FACTOR TEST-BOARD DESIGN IMPACT ON THERMAL IMPEDANCE MEASUREMENTS

scaa022a.pdf (77 KBytes) (Abstract)

9. LIVE INSERTION

sdya012.pdf (151 KBytes) (Abstract)

10. LOW-COST, LOW-POWER LEVEL SHIFTING IN MIXED-VOLTAGE SYSTEMS

scba002.pdf (48 KBytes) (Abstract)

11. LVC CHARACTERIZATION INFORMATION

scba011.pdf (114 KBytes) (Abstract)

12. METASTABLE RESPONSE IN 5-V LOGIC CIRCUITS

sdya006.pdf (192 KBytes) (Abstract)

13. PRINTED CIRCUIT BOARD LAYOUT FOR IMPROVED ELECTROMAGNETIC CAPATIBILITY

sdya011.pdf (145 KBytes) (Abstract)

14. RECENT ADVANCEMENTS IN BUS-INTERFACE PACKAGING AND PROCESSING

scza001a.pdf (64 KBytes) (Abstract)

15. SHELF-LIFE EVALUATION OF NICKEL/PALLADIUM LEAD FINISH FOR INTEGRATED CIRCUITS

szza002.pdf (118 KBytes) (Abstract)

16. STEAM-AGE EVALUATION OF NICKEL/PALLADIUM LEAD FINISH FOR INTEGRATED CIRCUITS

szza004.pdf (126 KBytes) (Abstract)

17. THE BERGERON METHOD A GRAPHIC METHOD FOR DETERMING LINE REFLECTIONS IN TRANSIENT

sdya014.pdf (177 KBytes) (Abstract)

18. THE BYPASS CAPACITOR IN HIGH-SPEED ENVIRONMENTS

scba007a.pdf (67 KBytes) (Abstract)

19. THERMAL CHARACTERISTICS OF SLL PACKAGES AND DEVICES

scza005b.pdf (100 KBytes) (Abstract)

20. THIN VERY SMALL OUTLINE PACKAGE (TVSOP) APPLICATION BRIEF

scba009c.pdf (353 KBytes) (Abstract)

21. TIMING MEASUREMENTS WITH FAST LOGIC CIRCUITS

sdya015.pdf (1727 KBytes) (Abstract)

DIGITAL PHASE-LOCKED-LOOPS (PLLS)

1. DIGITAL PLL DESIGN USING THE SN54/74LS297

sdla005b.pdf (598 KBytes) (Abstract)

INVERTERS

1. INTERFACING THE TLC5510 ANALOG TO DIGITAL CONVERTER TO THE TMS320C203 DSP

slaa029.pdf (541 KBytes) (Abstract)

2. INTERFACING THE TLC5540 ANALOG TO DIGITAL CONVERTER TO THE TMS320C203-80 DSP

slaa032.pdf (763 KBytes) (Abstract)

MONOSTABLE MULTIVIBRATORS

1. DESIGNING WITH THE SN54/74LS123

sdla006a.pdf (119 KBytes) (Abstract)

NON-INVERTING BUFFERS AND DRIVERS

1. AVC LOGIC FAMILY TECHNOLOGY AND APPLICATIONS

scea006a.pdf (148 KBytes) (Abstract)

2. TIMING DIFFERENCES OF 10-PF VERSUS 50-PF LOADING

scea004.pdf (47 KBytes) (Abstract)

OTHER DIGITAL LOGIC

1. DIGITAL PLL DESIGN USING THE SN54/74LS297

sdla005b.pdf (598 KBytes) (Abstract)

SINGLE GATES/FUNCTIONS

1. INTERFACING THE TLC5510 ANALOG TO DIGITAL CONVERTER TO THE TMS320C203 DSP

slaa029.pdf (541 KBytes) (Abstract)

STANDARD BUS SWITCHES

1. 5-V TO 3.3-V TRANSLATION WITH THE SN74CBTD3384

scda003b.pdf (44 KBytes) (Abstract)

2. LOW-VOLTAGE BUS-SWITCH TECHNOLOGY AND APPLICATIONS

scda005.pdf (42 KBytes) (Abstract)

3. SN74CBTS3384 BUS SWITCHES PROVIDE FAST CONNECTION AND ENSURE ISOLATION

scda002a.pdf (47 KBytes) (Abstract)

4. TEXAS INSTRUMENTS CROSSBAR SWITCHES

scda001a.pdf (49 KBytes) (Abstract)

STANDARD TRANSCEIVERS

1. AVC LOGIC FAMILY TECHNOLOGY AND APPLICATIONS

scea006a.pdf (148 KBytes) (Abstract)

2. NEXT-GENERATION BTL/FUTUREBUS TRANSCEIVERS ALLOW SINGLE-SIDED SMT MANUFACTURING

scba003c.pdf (66 KBytes) (Abstract)

UNIVERSAL BUS DRIVERS (UBDS)

1. LOGIC SOLUTIONS FOR PC-100 SDRAM REGISTERED DIMMS

smoa001a.pdf (118 KBytes) (Abstract)

2. SSTL FOR DIMM APPLICATIONS

scba014.pdf (55 KBytes) (Abstract)

3. TI SN74ALVC16835 COMPONENT SPECIFICATION ANALYSIS FOR PC100

scea007.pdf (54 KBytes) (Abstract)

4. TIMING DIFFERENCES OF 10-PF VERSUS 50-PF LOADING

scea004.pdf (47 KBytes) (Abstract)

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