MCU TECHNICAL MARKETING ENGINEERING				(512) 440-2990


October 21, 1987

Products affected:
MC68HC11A0
MC68HC11A1
MC68HC11A8
SC98XXX

Mask set:
B96D
B46E
B65H
B95T

    The MC68HC11 B96D mask set produced in Mesa, Arizona; the B46E mask produced
in Austin, Texas; the B65H mask produced in Aizu, Japan; and the B95T mask
produced in East Kilbride, Scotland are all equivalent mask sets.  The following
contains information concerning anomalies, changes, and user advice for these
mask sets.

    ERRATA:
    Use of slow edges on signals feeding the timer input capture or pulse
accumulator inputs is not recommended.	Use of buffers with edges faster than
100 nsec will prevent system noise generating false captures.

    Expanded mode Wait current is up to 15mA on the B96D mask due to a change
made to enhance multiplexed bus timing margins.  Single chip mode Wait current
is not affected.

    User updates of the SCI Baud Rate Control Register (BAUD) with the same
data during serial data transfers may cause errors on the byte being
transmitted/received.

    When the DLY bit in the OPTION register is set (logic 1) a clock failure
causes the Reset vector rather than the Clock Monitor vector to be fetched when
the clock restarts.  The user can get the proper Clock Monitor vector by
clearing the DLY bit in his initialization routine.  Peripheral devices
requiring several clock cycles to re-initialize after reset is released may be
affected as the E clock output is also inhibited during the clock restart delay.

    When the SPI is operating as a slave with CPHA = 1, and the SCK input is
asynchronous to the E clock, SPI transfers can fail such that SPIF is not set.
Occasionally, the next transfer after such a failure will result in an
improperly received data character.

    FUNCTIONALITY CHANGES:
    The use of the CONFIG register has been modified on the B96D, B46E, B65H,
B95T, and future mask sets.  On all previous mask sets, the CONFIG register
could be programmed or erased from any of the four operating modes.  On the new
masks, programming or erasing of the CONFIG register is restricted to the two
special modes, Test and Boot.  The CONFIG register cannot be modified in the
normal, single chip or expanded multiplexed modes.  Attempts by software to
program or erase the CONFIG register in these modes will be ignored.  This
change enhances the data security of the CONFIG register.

    Another change that appears on mask programmed B96D, B46E, B65H, B95T, and
future mask sets is that the security feature code was removed from the Boot
ROM on non-secure parts.  Only customers who wish to have the security bit
enabled will receive the bootloader with the appropriate security bit code.

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    USER INFORMATION:
    A new data sheet for the MC68HC11 series is now available.	The 1987 data
sheet can be ordered from your local Motorola sales office.  The document was
completely re-written to correct various errors, add information, and provide
better functional descriptions.

    An inadvertent write or erase of EEPROM can be caused by a program runaway.
Specifically, if the system has a slow power-down and the reset signal tracks
the VDD line (as does the external RC reset circuit suggested in the original
68HC11A8 data sheet), the CPU will eventually stop executing code properly, and
the program can jump to a section of code that may write or erase EEPROM.  The
only way to absolutely protect EEPROM data during power-down is to have the
device securely in reset.  In the development environment typical for the EVB
board, it was also possible to alter EEPROM due to a program runaway in user
code or during debug.  The new M68HC11EVB has been redesigned using the Motorola
MC34064P undervoltage sensing circuit to eliminate this.  See section 9 in the
new data sheet for more information.

    The on-chip RC oscillator should be enabled (by setting the CSEL bit in the
OPTION register) to program or erase the EEPROM when the operating frequency is
below 2 MHz.  Alternatively, the user may elect to increase the programming time
to 15 ms when the operating frequency is between 1 MHz and 2 MHz.  See section
3.5 and table 11.10 in the new data sheet for more information.

    The 68HC11 comes from Motorola with the CONFIG register programmed to
enable (or disable) on board memory and disable the COP feature.  For example:
	  MC68HC11A8  (or SC98xxx)    =$0F	ROM & EEPROM enabled
	  MC68HC11A1		      =$0D	EEPROM enabled
	  MC68HC11A0		      =$0C	ROM & EEPROM disabled

    Motorola is now offering custom factory programming of the CONFIG register
with the B96D, B46E, B65H and B95T masks if specified at the time of initial
order for a mask programmed SC device.	The order form in the new data sheet
includes a selection for the CONFIG contents.

    Current production units of the 68HC11A series are being tested at 25C and
85C and are expected to perform down to -40C except for the errata listed
above. Based on current reliability data, we expect EEPROM (68HC11A1/A8 devices
only) endurance failures to be less than 2% at 10,000 cycles at 25C or less
than 2% at 5,000 cycles at 85C.  We also expect the EEPROM data retention
failure rate to be less than 300 FITs at 55C or less than 26 FITs at 25C. (One
FIT is one failure in 10^9 device hours.  These figures assume an activation
energy of 0.7eV using a chi-square distribution at 90% confidence.)

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12. Functionality Change:  The MODB pin has been redefined on the A38P, A49N,
and all subsequent 68HC11A series masks.  The MODB input implements the special
modes (Test and Boot modes) with an active low level rather than the 1.8 times
VDD level used on the XC68HC11B series.  The extra high input level is no
longer required.  A new feature, VKAM (Keep Alive Memory supply), is shared
with the MODB pin to retain RAM contents during powerdown.  This feature
requires special voltage level pre-cautions on the current masks, but will have
fewer restrictions on the B46B mask set.



















































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