Frequently Asked Questions about the 68360 Last Modified: June 22, 1994 Introduction: In order to provide more technical information to our customers, we have compiled a list that contains helpful hints and often asked questions about the QUICC. We plan to update this list regularly so that we can get pertinent information out faster and more efficiently. We ask that you read over this list to become familiar with the format so that you may quickly find the answer your question. You are encouraged to reference this list, the user's manual, and errata before contacting your local field person with your question. Any new questions will be placed both in the heirarcy and in section 19, "New Questions". If you have any questions about the information contained in this list, please contact your local Motorola Field Representative. This list is available at the following locations The Motorola BBS (512) 891-3733 anonymous FTP bode.ee.ualberta.ca directory: /pub/motorola/mcu360 (note, the FTP site is picky about passwords. the easiest way to get through it is to enter Òusername@Ó at the ÒPassword:Ó prompt) Thank You. ***** New "feature" ***** Category 19 has been moved to the beginning of the file so that people who are familiar with the Frequently Asked Questions list do not have to scroll all the way to the bottom to find the new questions. Categories: 1. CPU32+ 2. SIM60 3. Memory Controller 4. IDMA Channels 5. SDMA Channels 6. Timers 7. Risc CP 8. SCCs a. Serial Interface b. UART Controller c. HDLC Controller d. HDLC Bus Controller e. Appletalk Controller f. BISYNC Controller g. Transparent Controller h. Ethernet Controller 9. SMCs a. UART Mode b. Transparent Mode 10. SPI 11. Parallel Ports 12. 040 Companion Mode/Slave Mode 13. Electrical Specs 14. Packaging Specs 15. Current Device Availability a. Parts/QUADS board availability 16. QUADS Board a. QUICCBug b. 360sw c. Documentation 17. Demo Code 18. Application Notes 19. New Questions/Information (Since May 18, 1994) ------------------------------------------------------------------------ 19. New Questions Current Errata Revision ----------------------- Device Errata for A.2 silicon May 9, 1994 Device Errata for B.2 silicon May 9, 1994 UM Errata February 21, 1994 Announcement ----------------------- A new file called Òapplications.infoÓ can be found on the FTP site and on the BBS. This file contains a list of the latest versions of all of the following documents and how to obtain them: UserÕs Manuals and Errata Microcode UserÕs Manuals and Errata Device Errata Development Board documentation, information, and errata Applications Notes Demo Code Demonstration Schematics This information exists for all Datacomm products: MC68360 Quad Integrated Communications Controller (QUICC) MC68302 Integrated Multiprotocol Processor MC68195 LocalTalk Adapter MC68824 Token Bus Controller MC68184 Broadband Interface Controller MC68185 Twisted Pair Modem MC68194 Carrierband Modem MC68605 X.25 Protocol Controller MC68606 Multi-Link LAPD Controller MC68840 Integrated FDDI MC68847 Quad ELM MC68838 Media Access Controller (MAC) MC68837 Elasticity Buffer and Link Management (ELM) MC68836 FDDI Clock Generator (FCG) MC68839 FSI MC68848 CAMEL MC68834 Stream Cipher Chip Therefore, sections 17 and 18 have been moved to this new file. *** Changed Answer *** Question: Is it possible to run the QUICC from a 10 MHz external oscillator and clock the CPU at 25 MHz? Answer: Yes. The system should be brought up with the MODCK pins set to 01. Once the system is running, disable the PLL, change the prescaler to 128 and the MF to 320, then re-enable the PLL. (This is all done in the PLLCR) ** However, the XFC filter capacitor value cannot accommodate both of these modes, therefore, the only way to do this is to bring up the QUICC with the PLL disabled (MODCK=00) and then set the MF, prescaler, and the PLLEN bit. However, the QUICC is not tested with the PLL disabled so we cannot guarantee this will work. Note that the part will be clocked at 10Mhz/2 while the PLL is disabled. *** Changed Answer #2 **** Question: I would like to use a QUICC and an 040. I am worried about excessive clock skew between the 040 and QUICC clock inputs. Answer: If you feed a 25 MHz clock in to QUICC and then use the output of CLKO2 as a 50 MHz input to the 040, we guarantee that it will meet the spec. Thus PCLK should be connected to CLK02 and BLCK should be connected to EXTAL. *** Note: There will be some skew between EXTAL and CLKO1 (the QUICCÕs bus clock) according to the updated UM specs. Therefore, you must take this skew into account when analyzing timing for the system. *** Changed Answer #3 *** Question: Can the internal QUICC bus masters use 040 bus mode? Answer: No. The QUICC internal bus masters use 030 bus mode. The QUICC memory controller can handle 030 bus mode or 040 bus mode. The mode is determined by assertion of TA* or AS* to start the cycle *** Therefore, if you wish to use your own memory controller, it must support both 030 and 040 bus cycles. Question: If BR* is asserted while the QUICC is in reset, will it return a BG* and delay the fetch of the stack pointer and program counter. Answer: Yes. However, BG* will be returned BEFORE the QUICC deasserts RESET(H/S)*. Therefore, you must wait until RESET(H/S) is deasserted before attempting to use the bus or else the memory controller, etc.. will not operate properly. Question: Will the QUICC exit BDM mode if RESETS* is asserted externally? Answer: Yes. There will be no signal through the BDM connector that this has occurred. Question: One page 2-8 of the 68360 UM, it says that our CAS0 line selects data bits 31-24, however DRAM modules usually call CAS0 to sel bits 7-0. Answer: Yes, our CAS descriptions are reversed from most DRAMs. Thus, be careful when you hook up the CAS lines to a DRAM. Question: When I disable the receiver and then re-enable the receiver of an SCC, I sometimes get a partial frame. Why? Answer: You should issue the ENTER HUNT MODE command immediately after you disable the receiver. This will flush the FIFO and close the current BD. Question: Currently, emulator manufacturers are only shipping probes that work with the PQFP package. Do you know when they will be shipping probes for the CQFP? Answer: To our knowledge, all emulator manufacturers are working on CQFP probes. There are some manufacturers who do have CQFP probes already. The best bet is to call around to all of the emulator makers to find out who is currently shipping. Question: Does the QUICC generate parity on the parity pins even if Parity Checking is not enabled? Answer: Yes Question: Will the IDMA continue to function properly if the SSIZE or DSIZE bits are set differently than the actual port size? (either in the MEMC or External DSACK) Answer: It will not function properly in the general case. It is recommended that SSIZE/DSIZE will show the real port size. In the following cases, however, it will still work: 1.If SSIZE/DSIZE is smaller then actual size it will work, but will be less efficient. 2.If SSIZE/DSIZE=WORD & actual port size = BYTE it will work (although not very practical). 3.If SSIZE/DSIZE=L, it will work properly only if actual port size is long. Question: I have some non-Motorola 72 pin SIMMS. Can I use them in my QUADS board? Answer: Yes. However the QUADS Board detects the type of used DRAM-SIMM using detect pins on the 36-bit module. A table of the supported modules is included in the M68360 QUADS Hardware Users Manual chapter 4.6 page 25. The first column of this table lists the configuration of the PDS pins. This configuration does not neccessarily work with DRAM-SIMMs from other vendors. For example, the QUADS Board will not work with Texas SIMMs without modification of the SIMMs. But this modification is very easy: just configure the PDS pins of your SIMM the way it is described in this Table 4-1. Hint: 0 is a short between the PDS Pin and GND, 1 means leave the PDS Pin open. In addition, you will have the change the page size in the GMR register on the SLAVE QUICC to reflect the new DRAM size. The software doesnÕt automatically change this setting. A too-small page size is not a problem on Rev B silicon but does cause false page-hits on Rev A.2 silicon as mentioned in the Device Errata. ------------------------------------------------------------------------ 1. CPU32+ Question: What is the best case interrupt latency for the QUICC? Answer: The CPU32+ has a best case interrupt latency of approximately 39 clocks. Add 3 clocks for the SIM60 interrupt arbitration hardware. Question: Does the CPU32+ do longword fetches? Answer: Yes, CPU32+ does longword fetches. It will, however, detect the port width (by checking DSACK size after fetch) and do fetches accordingly until DSACK size changes. Question: Is there a freeware assembler for the CPU32? Answer: Yes, it is called AS32 and can be found on the Motorola Freeware BBS. (512) 891-3733. Question: Can I change the CPU32+ to a higher bus arbitration priority so that it will get the bus during a high priority task? Answer: Yes. The trick is to program BCLRISM0-2 (in the MCR) so once the interrupt level is higher than the level programed on BRLRISM0-2, BCLRO will go low. You can use this pin to gate off BR coming into the 360. Thus, the CPU will not give away the bus while BCLRO is asserted. In addition, you might want to program the DMA interrupt mask level lower then that of the CPU interrupt request. This will give the CPU bus arbitration priority over the DMA. Question: If BR* is asserted while the QUICC is in reset, will it return a BG* and delay the fetch of the stack pointer and program counter. Answer: Yes. However, BG* will be returned BEFORE the QUICC deasserts RESET(H/S)*. Therefore, you must wait until RESET(H/S) is deasserted before attempting to use the bus or else the memory controller, etc.. will not operate properly. ------------------------------------------------------------------------ 2. SIM60 Question: My 68360 doesn't seem to want to enter slave mode. Sometimes it will enter slave mode but it does not function properly when it does. Answer: A special reset sequence is needed to put the chip into slave mode. See the Device Errata (A.2) for more details. This is fixed in Revision B of the part. Question: Does the DRAM controller continue to refresh DRAM while the processor is stopped in Background Debug Mode? Answer: Yes (assuming that the DRAM controller was programmed to do DRAM refresh of course). Question: Can I use a BDM connector if the QUICC is in slave mode Answer: No. Since there is no CPU to control with a BDM connector. (The 680x0 line does not support Background Debug Mode) Question: Can a 302 be used as a slave to a QUICC Answer: Yes, it would appear to the 302 that it was talking to a 25 MHz 020. Be sure to follow the 302 device errata related to using an Asynchronous Bus. Question: I can't seem to read or write MBAR in Master Mode. Answer: MBAR is actually in CPU space, not in user or supervisor space. Thus you must follow the procedure on page 6-30 of the UM. Question: What is the difference between RESETS and RESETH? Answer: RESETS was implemented to allow for a reset to occur that would still retain the current settings of the SIM60 registers, thus retaining the chip select mapping and DRAM Refresh during a reset. The reset values for both RESETS and RESETH are shown in the memory map on pages 3-5 through 3-11. When an "H" is shown after the reset value, it means that the register is only reset by a hard reset. Question: I am trying to use the Show Internal Cycles feature but I am not seeing any internal cycles on my logic analyzer. Answer: Make sure that the logic analyzer is triggering off of DS* rather than AS*. In Show Cycles Mode, AS* is not toggled. In addition, it is possible that state mode of the logic analyzer will not work due to the timing of DS* and the Data and Address Busses. If you are having problems, try wave mode. Question: If I assert RESETS* and RESETH* at the same time, will both be set in the status register? Answer: Both RESET pins are asynchronous, thus they may be recognized on different clocks. If they are recognized on the same clock, or if RESETH* is recognized first, both the EXT bit and the SRSTP bit will be set. If RESETS* is recognized first, the register will reflect only a hard reset. Question: Is it possible to run the QUICC from a 10 MHz external oscillator and clock the CPU at 25 MHz? Answer: Yes. The system should be brought up with the MODCK pins set to 01. Once the system is running, disable the PLL, change the prescaler to 128 and the MF to 320, then re-enable the PLL. (This is all done in the PLLCR) ** However, the XFC filter capacitor value cannot accommodate both of these modes, therefore, the only way to do this is to bring up the QUICC with the PLL disabled (MODCK=00) and then set the MF, prescaler, and the PLLEN bit. However, the QUICC is not tested with the PLL disabled so we cannot guarantee this will work. Note that the part will be clocked at 10Mhz/2 while the PLL is disabled. Question: Is DPRAM cleared on hard reset? Answer: No. Question: Are the IRQx pins edge sensitive or level sensitive? Answer: The IRQ1-6 pins are level sensitive, the IRQ7 pin is edge sensitive. See the Errata at the end of this document for more timing information. In master QUICC, the IRQ pins have to be asserted until the termination of the IACK cycle (i.e. until IACK AS* negation). The signal can be reasserted immediatly. In fact, except for IRQ7 it can be asserted continuously. The second interrupt (i.e. iACK cycle) will be generated when the interrupt mask in the CPU SR is changed to a lower value. This ususually happens when the RTE instruction is executed. It can be done also by changing the SR value explicitly. IRQ7 is edge sensitive. In order to generate another level 7 interrupt, the IRQ7 must be negated after the IACK cyle is terminated (AS* negation). It should be non active for at least 3 clocks before its re assertion. After re assertion of the signal, the interrupt is recognized and acknowledged, no matter what the value of the SR (NMI interrupt actually). Question: Will Halt disable just the CPU or the whole QUICC? Answer: Assertion of HALT neither disables the CPU nor prevents DRAM refresh cycles. If it is asserted by an external device (i.e. driven from outside the QUICC), it freezes the external bus state after cycle termination. After HALT* negation, the QUICC will continue its operation. If HALT* is driven by the QUICC itself, it indicates a Double Bus Fault error and CPU is stopped. This can overcome only by RESETS/RESETH assertion. In SLAVE config., HALT* tells the QUICC to relinquish the bus after cycle termination. REFRESH cycles are not normal bus cycles and thus are unaffected. However, if HALT* assertion prevents termination of previous access, such as the middle of an IDMA packing, the refresh waits for this cycle to be finished. Free Advice: When operating in slave or companion mode the MBAR should not be configured to locate the internal memory of the QUICC in a region which requires the top nibble to be anything other than 0000. A28-A31 are internally pulled down after reset until PEPAR is written (see note on page 6-50 of the UM). This can be overcome by first writting to MBAR with MSB=0x0X, then writing to PEPAR to enable A31-A28, and then changing MBAR to the new value. Question: When using a 25 MHz external oscillator, the PITR register does not allow PIT interrupts in the range of 5ms to 10ms. How can I generate a PIT interrupt in this range? Answer: The best way is to divide your interrupt period by two and then insert a semaphore in your service routine so that "work" is only done every other interrupt. Question: When I power up the QUICC, CLK01 doesn't output a waveform as is shown on page 4-70. Answer: This is an error in the manual. Page 4-70 shows CLK01 being enabled at VCO lock. This will only occur if the MODCK pins are programmed to 10 or 11. It will not occur if the MODCK pins are programmed to 01. Question: What state do the RAS and CAS lines go into after power-up prior to the DRAM controller being programmed? Answer: The RAS and CAS lines are driven High after power up. Therefore you need isolation gates in order to connect together the RAS/CAS lines from two QUICCs. Question: I sometimes get corrupted vectors during interrupt acknowledge cycles. Answer: Check your MBAR programming. You should set MBAR to mask out CPU space accesses (set bit 8 of MBAR). If you don't do this, IACK cycles (which occur in CPU space) can look like accesses to internal memory and cause contention. Question: Are there pullups on the CONFIG pins? Answer: Yes, there are pullups on the CONFIG pins. Thus, a 10K pulldown will not be adequate to pull down a CONFIG pin. You will have to actively drive it down through an open drain driver. Note: Since the CONFIG pins are only valid during the reset process, a PAL can be very useful at driving the CONFIG pins during reset while leaving their non-reset functionality intact. Question: What is the difference between the VccSYN and Vcc pins? Same with the GndSYN and Gnd pins? Answer: The xxxSYN pins provide power and ground to the clock synthesizer. If you are using a crystal circuit, you must exercise great care in isolating the VCCsyn and GNDsyn pins from the Vcc and GND signals. Failure to do so could result in the PLL unlocking. Question: Should unconnected pins be terminated? Answer: All input pins or I/O pins that can become input pins should be terminated. For example, if you are not using Parity in your system but you have an external master, the parity pins should be terminated because an external master cycle will cause the parity pins to become inputs. Helpful Advice: If you have a slow Vcc ramp up time at power-up, your circuit may encounter problems. Reason: The QUICC will deassert RESETH* and fetch the opening vector 512 clocks after Vcc has reached approximately 2.0V. Thus, with a 25Mhz system clock, the QUICC will deassert RESETH* 20 microseconds after Vcc has reached 2.0V. If Vcc has a slow ramp up time, Vcc may not have reached 4.75 Volts at the time that RESETH* deasserts. If this occurs, the QUICC will fetch the initial vectors from memory, but memory will not be functional yet due to low Vcc and will not provide the boot vectors, thus the CPU32+ will double bus-fault and halt. Two seconds later, the software watchdog with reset the chip. If your power supply has a slow ramp up time, you will have to put reset circuitry in your board to prevent the QUICC from coming out of reset by leaving RESETH* asserted until Vcc reaches 4.75V. Question: Will the QUICC exit BDM mode if RESETS* is asserted externally? Answer: Yes. There will be no signal through the BDM connector that this has occurred. ------------------------------------------------------------------------ 3. Memory Controller Question: If the QUICC is being used along with a external master. When this external master is accessing DRAM when does the QUICC determine the end of cycle. Is it the negation of CAS*, the negation of DSACK*, or the negation of AS*. Answer: It depends on the SYNC bit. If SYNC=0 then DSACK* rises after AS*,thus it is the negation of AS*. If SYNC = 1 it is according to the bus cycle. i.e. S5 (which is determined according to DSACK* assertion settings in the memory controller configuration registers). Question: If the BSTM and SYNC is set for async operation (both set to 0). What will the parity bits indicate on output from the QUICC.? Answer: Parity lines will not show the correct value until the next bus cycle, thus the parity lines are unusable. Question: In Page Mode operation, will RAS* be deasserted if the next bank hit is an SRAM bank? Answer: No. RAS* for that bank will only be deasserted when there is a miss on that particular DRAM bank, another DRAM is accessed (because there are only 4 CAS lines), or a processor Exception occurs. Question: What do the WE* lines do if the user programs the Memory Controller to external DSACK*? Answer: The WE* lines will be set to the system bus width, not memory width. Question: Are the DSACK signals generated by the memory controller shown on the DSACK* pins? Answer: Yes, except for fast termination cycles and internal bus cycles (even when Show Cycles is enabled) Question: If the memory controller is set up for a DRAM bank with external DSACK, will the CAS Address be valid until DSACK* is externally generated? Answer: Yes Question: What is the timing of the SIZ lines? Answer: The SIZ lines follow the same timing as the FC lines and the address lines (spec 150). Question: For internal masters, will the timing relax from TRLXQ in the Base Register occur regardless of the state of the SYNC bit? Answer: The SYNC bit has NO effect on internal accesses. To summarize: MASTER SRAM/DRAM sync TRLX valid ------- ---------- ---- ----------- EXT SRAM 0 no EXT SRAM 1 yes EXT DRAM 0 yes EXT DRAM 1 yes INT SRAM x yes INT DRAM x yes Question: In what order should I program the Option and Base Registers in the Memory Controller? Answer: If you are reprogramming the boot chip select (CS0), you should program the base register first. For all other chip selects, you should program the option register first. Question: How will the WE* signals change in Rev. B.? Answer:1) Rev. B will allow the WE signals to be directly connected for non-32 bit wide ports (as programmed in the memory controller). Thus, WE0* will be asserted when A(1:0)=00 in a 32 bit wide port, when A(1:0)=x0 in a 16 bit wide port, and when A(1:0)=xx in an 8 bit wide port. As before, if external DSACK is used, it will default to the bus size (as set in the 16BM pin). Question: Will the DRAM Controller generate refresh cycles when in BDM mode? Answer: yes Question: Will external assertion of the DSACK* signals terminate a cycle that would have been terminated by the memory controller? Answer: Yes. Therefore, you should normally have external circuitry provide DSACK* only for memory blocks that are programmed for external DSACK* generation or for memory blocks that are not handled by the memory controller. Care must be taken not to have DSACK* driven by external circuitry at the same time that DSACK* is driven internally. (e.g. Don't have the memory controller assert DSACK* after 15 wait states and have the external circuitry also assert DSACK* after 15 wait states. Always use open-collector device to externally drive DSACK*) Question: Do the WE* lines assert if an access is made to a memory area not served by the internal memory controller? Answer: Yes. They assert as if the memory is as wide as the bus (depending upon the configuration of the 16BM pin) Question: One page 2-8 of the 68360 UM, it says that our CAS0 line selects data bits 31-24, however DRAM modules usually call CAS0 to sel bits 7-0. Answer: Yes, our CAS descriptions are reversed from most DRAMs. Thus, be careful when you hook up the CAS lines to a DRAM. Question: Does the QUICC generate parity on the parity pins even if Parity Checking is not enabled? Answer: Yes ------------------------------------------------------------------------ 4. IDMA Channels Question: Will the assertion of DONE on an IDMA in buffer chaining mode cause the IDMA to end the operation on the current buffer and chain to the next available buffer, or will this cause the termination of the chain? Answer: It will cause termination of the chain. The current BD will be closed, the Start bit in the CMR will be cleared, and the Reset bit will be set. The User's Manual is incorrect. Question: If a bus error occurs on an IDMA cycle, does the CPU take the Bus Error Exception? Answer: No. The CPU does not participate at all. If the CPU is not the bus master, it ignores the BERR cycles. A bus error is reported in the CMR by the BES and BED bits (Bus error on source or Bus Error on dest). It will generate an interrupt to the CPU if the corresponding bit in the CMAR is set. Question: If I am using the IDMA external request burst mode with fast termination cycles, why do I get an extra cycle? Answer: The IDMA recognizes the negation of DREQ* on the falling edge of S2 (page 10-64). Since that clock phase does not exist in a fast termination cycle, the negation will not be recognized until the next bus cycle and therefore you will get an extra transfer. (not just an extra bus cycle) Question: Can I use IDMA single address mode between an external peripheral and DPRAM? Answer: No. You can only use singal address transfer mode between an external peripheral and external memory. In order to transfer between DPRAM and an external peripheral, you have to use dual address mode. Question: Will the IDMA continue to function properly if the SSIZE or DSIZE bits are set differently than the actual port size? (either in the MEMC or External DSACK) Answer: It will not function properly in the general case. It is recommended that SSIZE/DSIZE will show the real port size. In the following cases, however, it will still work: 1.If SSIZE/DSIZE is smaller then actual size it will work, but will be less efficient. 2.If SSIZE/DSIZE=WORD & actual port size = BYTE it will work (although not very practical). 3.If SSIZE/DSIZE=L, it will work properly only if actual port size is long. ------------------------------------------------------------------------ 5. SDMA Channels Question: Will the swapper correctly make a long word into Intel format? Answer: Yes. It will correctly swap words and long words. It will not properly swap long words in 16-bit bus mode however. ------------------------------------------------------------------------ 6. Timers Question: I am using the PIT timer and am seeing the interval divided by 128. Why is this happening? Answer: This is coverend in the current UM Errata under SPCLK. The PIT is timed from SPCLK which is clocked at EXTAL/128 when the EXTAL input is greater than 10 Mhz (i.e. MODCK1-0 = 01) ------------------------------------------------------------------------ 7. Risc CP Question: If we use a ram microcode, how much space does that leave in the internal DPRAM for BD's, etc... Answer: If a "small" (512 byte) microcode is used, then you will have from DPRBASE+$200 to DPRBASE+$5FF (1024 bytes) for BDs. If a "large" (1024 byte) microcode is used, then you will have from DPRBASE+$400 to DPRBASE+$5FF (512 bytes) for BDs. If you are not using all of the facilities of the chip (i.e. not using an SCC, or an IDMA, or an SMC, or the SPI) it is possible to get as many as 128 contiguous bytes for BD space. Question: How can I tell which version of the QUICC I am using? Answer: In order to determine the microcode revision number by checking the "Rev_num" field detailed on page 7-6 of the QUICC UM. The word will be $0001 for Rev A silicon and $0002 for Rev B silicon. Question: Does a CP Reset happen when the QUICC is reset? Answer: Yes. The CP will be reset by a hard reset, a soft reset, or by issuing the Reset command in the CR. Question: Can a Token Ring microcode be written for the QUICC? Answer: No. The QUICC hardware cannot currently support Token Ring. ------------------------------------------------------------------------ 8. SCCs Question: My SCC won't transmit and/or receive. Answer: Except for the protocol specifics, all SCCs are programmed in a very similar way. Thus, the following steps should be taken regardless of the protocol. If the channel neither transmits nor receives: 1) Try the channel in loopback mode (set in the GSMR) 2) Is the SDCR register properly configured? 3) Have you issued the INIT TX AND RX PARAMETERS command after setting RBASE and TBASE? 4) Double-check your clocking source in the SICR register 5) Check that the BRGCx register is properly configured to a valid data rate If the channel only operates in loopback mode: 1) Be sure that all parallel port bits for the NMSI interface are properly configured in Port A and Port C (tables 7-16 and 7-18) 2) If you have set your parallel ports for external CTS/CD, be sure that they are asserted (low) when you want to Transmit/Receive Question: How long is the delay from when the ready bit in the buffer descriptor is set and when the first bit is actually transmitted? Answer: Between 0 and 32 serial clocks. See section 7.10.5 of the MC68360 User's Manual for information on how to cut down the latency. Question: When I disable the receiver and then re-enable the receiver of an SCC, I sometimes get a partial frame. Why? Answer: You should issue the ENTER HUNT MODE command immediately after you disable the receiver. This will flush the FIFO and close the current BD. ------------------------------------------------------------------------ 8a. Serial Interface Question: Can I gate the clock into TCLK and RCLK Answer: Yes. This will allow you to either 1) Instantly turn off the transmitter or 2) Selectively receive data. On the receive side, realize that the data will not move out of the FIFO into the Buffer until you give it enough clocks to shift out. The small or large FIFO settings have no affect on the number of clocks before the data is placed in the BD. Question: Does L1SYNC have to be one clock wide or can it be a longer pulse. Answer: The TSA only looks at the rising edge of L1SYNC. Thus the pulse can be longer than 1 clock cycle. Question: Can I use the recovered clock from the DPLL as the transmit clock? Answer: No. There is no way to use the recovered clock to drive the transmitter. It can only use an input pin or a baud rate generator. Question: How close does the input clock to the DPLL need to be to the actual data rate? Answer: In 8x mode, within 12.5% assuming no jitter. In 16x mode, within 6.25% assuming no jitter. In 32x mode, within 3.125% assuming no jitter. ------------------------------------------------------------------------ 8b. UART Controller Updated SCC Performance Numbers Four SCCs can run UART: - No control characters => running up to 762KHz - 2 control characters => running up to 681KHz - 3 control characters => running up to 643KHz - 4 control characters => running up to 613KHz - 8 control characters => running up to 500KHz If the user exceeds theser rates, the channel will NOT generate underrun or framing error, the transmitter will simply stop transmitting for a period of time. ------------------------------------------------------------------------ 8c. HDLC Controller Question: Why am I not getting RXF interrupts after I receive an HDLC frame? Answer: Check the RFTHR setting in the HDLC memory map. This word determines how many frames will be received by the HDLC controller before it sets the RFX bit in the event register. If RFTHR is accidentally set to $0000, then 64K frames will be received before the RXF interrupt will occur. ------------------------------------------------------------------------ 8d. HDLC Bus Controller Question: Can I use Manchester encoding to send the clock with the data? Answer: No, the collision algorithm will fail unless standard NRZ is used. Question: How can I tell when the QUICC is retransmitting in HDLC bus mode? Answer: In HDLC bus mode, the QUICC hides details of collisions and retransmissions from the user software and the user is not informed of any collisions. Provided that collisions occur during transmission of the first two buffers of a frame, the CP will handle each collision and re-transmit the whole frame automatically. The user is not informed of this even if the QUICC has to try retransmitting the frame many times. There are no interrupts or event bits for collisions. The only way the user software can observe collisions is by monitoring the RETRC counter. Question: If the DRT bit is set to disable the receiver when transmitting and the transmitted frame "collides" with a frame destined for that station, will the frame be received? Answer: No. Thus, you should not use DRT in HDLC Bus Mode. You should use address filtering instead. ------------------------------------------------------------------------ 8e. Appletalk Controller ------------------------------------------------------------------------ 8f. BISYNC Controller Updated SCC Performance Numbers Four SCCs can run BISYNC: - No control characters => running up to 430KHz - 2 control characters => running up to 390KHz - 3 control characters => running up to 373KHz - 4 control characters => running up to 357KHz - 8 control characters => running up to 305KHz ------------------------------------------------------------------------ 8g. Transparent Controller Question: I can't get the SCC to recognize the CD/CTS pins in external sync mode. Answer: The CD/CTS pins behave as follows: 1) Internal Loopback mode - The pins are ignored. The Transmitter and Receiver are instantly synced. 2) Sync mode is pulse - The sync signals are edge sensitive ... 3) Sync mode is envelope - only the receiver is edge sensitive. The reason: CTS can be active low all the time or used as a I/O (RTS is the envelope of the frame). CD should be edge sensitive in order not to synchronize in the middle of a frame (for example after reset). Question: Is there any way to get the Transparent Controller to ignore synchronization all together? Answer: Yes. The best thing to do is to tie a parallel I/O pin to the CTS and CD lines. Then after you enable the receiver and transmitter, provide a falling edge by manipulating the I/O pin in software. Another possibility is to enable the receiver and transmitter for the SCC in loopback mode and then change the GSMR diag mode bits to 00 while enabled. Question: When using transparent mode with a time slot assigner, should envelope mode (CPD=0) be used or pusle mode (CDP=1)? Answer: The channel should be programmed CDP=1 (and SYNL = 00). Question: When the REVD bit in the GSMR is set, will the byte order change or just the bit order? Answer: Just the bit order. ------------------------------------------------------------------------ 8h. Ethernet Controller Question: Which SCC do I use to run Ethernet? Answer: You can use any SCC for Ethernet. It is suggested that you use SCC1 due to its larger FIFO. Question: Can I run more than one Ethernet Channel? Answer: Yes, the QUICC is capable of running two 10 MBps Ethernet Channels. In that case, the second channel should be SCC2 but may be any of the other SCCs. Question: Can I run full-duplex Ethernet? Answer: Yes, you can use 1 SCC for Transmit and another SCC for Receive. Connect the SIA RxD, RCLK and RENA signals to one SCC, and TxD, TCLK and TENA to the other SCC. CLSN should not be used. This assumes that your transceiver can handle full-duplex Ethernet. In Rev B of the part, you will be able to use 1 SCC for both Transmit and Receive. Question: How can I tell an "EN" part from a non "EN" part? Answer: One way to detemine if the part is a EN360 is to set the SCC to Ethernet mode and set TEN=0. Then read the RTS_ (TENA) pin. If it is zero, it is a EN360 part, if not it's a plain 360. Question: I have a QUADS board and I can't seem to get the demo code for Ethernet to work. Answer: Be sure to use the "ESLAVE.ASM" code and not the "ETHN_EX1.ASM" code. Read the note at the top of the "ESLAVE.ASM" code. Question: When I use the QUADS board in Ethernet mode, the LEDs don't light up. Answer: The LEDs on the board are connected to the EEST (which may or may not be on your board) and thus may not light up even though the interface is working. Question: Can I use the EEST for both 10Base-T and 10Base-2? Answer: You can hook a National DP8392 or AMD AM7996 to the AUI port of the EEST to get 10Base-2. Question: I notice that the schematics for connecting the QUICC to the EEST are different in the QUADS documentation than in the EEST Manual. Which is correct (better)? Answer: You can choose either one. There is no "better" method. Question: If I am using two Ethernet channels, can I use two CAMs? Answer: You can use the second CAM to assert the RJECT* pin, but you cannot use the TAG function on the second channel. Question: I have a QUADS board with an EEST on it rather than the old SIA and am having problems. Is there something wrong? Answer: It may be your power supply. There is a voltage drop across the fuse which may lower the voltage enough to make the EEST nonfunctional. You should measure the supply voltage AFTER the fuse to insure that the supply voltage is close to 5V (the part is spec'ed to 4.75V) ------------------------------------------------------------------------ 9. SMCs Question: I am having problems running UART mode on the SMCs. Answer: There are currently many problems with SMCs running UART. Check the device errata (rev A.2) for more information. Question: I would like to use the SMCs in UART mode on Rev A.2 silicon. Is there a way to work around all of the errata that are listed in the Device Errata? Answer: Working around the problem may be difficult, but the best way is to use the microcode patch that is available from Motorola. This patch loads into DPRAM and takes up the area from DPRBASE+$000 to DPRBASE+$1FF and DPRBASE+$600 to DPRBASE+$6FF. Once the patch is properly installed, all of the errata listed on the current Rev A.2 device errata are fixed. ------------------------------------------------------------------------ 9a. UART Mode ------------------------------------------------------------------------ 9b. Transparent Mode ------------------------------------------------------------------------ 10. SPI ------------------------------------------------------------------------ 11. Parallel Ports Question: In the manual, it states that PADIR should be set to 0 (input) and PAPAR should be set to 1 in order to get the signals RXD1 and TXD1 out. Shouldn't PADIR be set to 1 (output) for bit 1 to get TXD1 out? Answer: No. PADIR only means direction when the pin is set up to be a general purpose I/O pin. Follow the tables on pages 7-351, 7-356, and 7-358 for instructions on how to set up the pins to be a certain signal. Question: What is the transfer rate for the PIP? Answer: The preliminary transfer rate for the PIP is 625 Kb/sec, assuming 8-bit transfers at 25 MHz. Question: If I have two QUICCs connected together via their parallel ports, and one QUICC is powered on and the other one isn't, is there any danger of damage to the unpowered QUICC? Answer: if Vcc in the unpowered QUICC is allowed to float, applying power to Centronics pins is fine. If Vcc is pulled low on the unpowered board, it will hurt the part. Question: If I have two QUICCs connected together via their parallel ports, and one QUICC is powered on and the other one isn't, is there any danger of damage to the unpowered QUICC? Answer: if Vcc in the unpowered QUICC is allowed to float, applying power to Centronics pins is fine. If Vcc is pulled low on the unpowered board, it will hurt the part. ------------------------------------------------------------------------ 12. 040 Companion Mode/Slave Mode Question: I would like to use a QUICC and an 040. I am worried about excessive clock skew between the 040 and QUICC clock inputs. Answer: If you feed a 25 MHz clock in to QUICC and then use the output of CLKO2 as a 50 MHz input to the 040, we guarantee that it will meet the spec. Thus PCLK should be connected to CLK02 and BLCK should be connected to EXTAL. *** Note: There will be some skew between EXTAL and CLKO1 (the QUICCÕs bus clock) according to the updated UM specs. Therefore, you must take this skew into account when analyzing timing for the system. Question: Does the DRAM controller support interleaved memory in 040 companion mode to allow 2-1-1 bursts. Answer: No. You would have to build your own memory controller for those banks that you wish to interleave. Question: Can the memory controller use Page Mode in 040 companion mode. Answer: No. Any memory bank that can be accessed by the 040 cannot use page mode. Question: In the A.2 Device Errata, it says to enter slave mode, the config pins should be set to master mode until "a few clocks" after the PLL locks. How many clocks is "a few"? Answer: 10 clocks is a good number to use. Question: How should I tie off FC3 in a 360/030 design? Answer: For a QUICC/030 design FC3 on the QUICC should be pulled down through a 10K. This should be added to fig 9-27. If this is not pulled down then you can't access the MBAR on the QUICC, since a CPU space access requires 0111 on the FC lines. Question: Can the internal QUICC bus masters use 040 bus mode? Answer: No. The QUICC internal bus masters use 030 bus mode. The QUICC memory controller can handle 030 bus mode or 040 bus mode. The mode is determined by assertion of TA* or AS* to start the cycle *** Therefore, if you wish to use your own memory controller, it must support both 030 and 040 bus cycles. Question: Do you have any recommendations on how to perform the config pin cycling that is required to get Revision A.2 parts into slave mode? Answer: You can use the PAL equations that are located in section C.4 of the QUADS Hardware Manual. ------------------------------------------------------------------------ 13. Electrical Specs Question: What is the derating factor for the QUICC pins? Answer: At this time we do not have that information. Question: Are the theta-JA and theta-JC ratings available yet? Answer:Thermal Resistance-Junction to case PQFP theta-JC 9.7 ¡C/W PGA theta-JC 3 ¡C/W Thermal Resistance-Junction to Ambient PQFP theta-JA 35.9 ¡C/W (still air) 30.4 ¡C/W (100ft/min) 28.0 ¡C/W (200ft/min) 23.8 ¡C/W (400ft/min) CQFP theta-JA 27.4 ¡C/W (still air) PGA theta-JA 22.0 ¡C/W Question: Do we have updated power specs? Answer: Char. Symbol Sys.Clk.Frq. BRGCLK SyncCLK Typ Max Unit Normal1 PD 25 MHz 25 Mhz 25 MHz 300 (***) mA Normal2 PD 25 MHz 25 Mhz 25 MHz 250 - mA Normal3 PD 25 MHz 25 Mhz 25 MHz 180 - mA Normal1 = All blocks on chip working at full frequency and power. Normal2 = Same as Normal1, but CPU32+ is disabled. Normal3 = Same as Normal1, but CPU32+ and both IDMAs are disabled. Normal2 and Normal3 do not have Max values, because these situations are not tested for each device, but are included for reference purposes only. (***) This value will be finalized soon. For now, use 450mA until we know for sure. Question: Do you have derating information for the 360? Answer: K-factor for decreasing load (less then 100pf) = 0.2 [ns/10Pf] K-factor for increasing load (more then 100pf) = 0.6 [ns/10pf] Question: Can the QUICC drive CMOS circuits? Answer: No. We spec min Voh = 2.4 V and CMOS requires over 4 V. ------------------------------------------------------------------------ 14. Packaging Specs Question: Who manufactures sockets for the QUICC? Answer: For PGA sockets, contact AMP. For PGA to QFP adapters, contact: Emulation Technology - (408) 982-0660 ISI - (805) 581-5626 Question: Currently, emulator manufacturers are only shipping probes that work with the PQFP package. Do you know when they will be shipping probes for the CQFP? Answer: To our knowledge, all emulator manufacturers are working on CQFP probes. There are some manufacturers who do have CQFP probes already. The best bet is to call around to all of the emulator makers to find out who is currently shipping. ------------------------------------------------------------------------ 15. Current Device Availability a. Parts/QUADS board availability We are currently sampling both backages of the 68360 and QUADS board. For specific information on part availability and lead times, call your local Motorola sales office. ------------------------------------------------------------------------ 16. QUADS Board Question: I would like to design a board which will interface to the QUADS board. What are the dimensions of the board? Answer: The QUADS board is the same width as a VMEBus card and the connectors are in the same position (though are the reverse gender). For specific dimensions, contact the Data Communications Group. Question: What are the manufacturer names and part numbers for the connectors on the QUADS board? Answer: P1 and P2 - Manufactured by ELCO part number 26 8477 096 002 025 these are DIN 96 pin right angled female connectors The opposite DIN 96 pin right angled male connectors are: 1. Wire-wrap connector, ELCO part number 16 8457 096 004 025 2 connectors are supplied with each QUADS. 2. PC board connector, ELCO part number 16 8457 096 002 025 ELCO Corporation Huntingdon Industrial Park Huntingdon, PA 16652 Phone (814) 643-0700 P11 - 5v power connector. The 3 terminal socket is manufactured by Wieland Bamberg part number 8113S 253303353 The required 3 terminal plug is Wieland Bamberg part number 8113B 253200353 P12 - 12v power connector. The 2 terminal socket is manufactured by Wieland Bamberg part number 8113S 253303253 The required 2 terminal plug is Wieland Bamberg part number 8113B 253200253 Wieland Industrie D-8600 Bamberg Brennerstrasse 10-14 Germany US Phone # is 919-259-5050 US Fax # is 919-259-3691 Question: What Chip Selects and Interrupt pins are available on the QUADS board? Answer: Chip Selects 1-6 are available from the master from P2. IRQ lines 1-7 are available on P2. If you wish to have external interrupts, you will have to make sure that the slave is not going to generate that level of interrupt. Question: I have some non-Motorola 72 pin SIMMS. Can I use them in my QUADS board? Answer: Yes. However the QUADS Board detects the type of used DRAM-SIMM using detect pins on the 36-bit module. A table of the supported modules is included in the M68360 QUADS Hardware Users Manual chapter 4.6 page 25. The first column of this table lists the configuration of the PDS pins. This configuration does not neccessarily work with DRAM-SIMMs from other vendors. For example, the QUADS Board will not work with Texas SIMMs without modification of the SIMMs. But this modification is very easy: just configure the PDS pins of your SIMM the way it is described in this Table 4-1. Hint: 0 is a short between the PDS Pin and GND, 1 means leave the PDS Pin open. In addition, you will have the change the page size in the GMR register on the SLAVE QUICC to reflect the new DRAM size. The software doesnÕt automatically change this setting. A too-small page size is not a problem on Rev B silicon but does cause false page-hits on Rev A.2 silicon as mentioned in the Device Errata. ------------------------------------------------------------------------ 16a. QUICCBug ------------------------------------------------------------------------ 16b. 360sw Question: When I attempt to run "360sw", it doesn't run. I just get an error. Answer: Two things may be happening. 1) Try it again. 360sw doesn't work the first time you run it after a power-on reset. It will work after that. 2) Do an MD b0000;di. If the code is garbage, it means that you have not programmed your flash. Follow the directions in the start.txt document that you received on disk with your QUADS board. ------------------------------------------------------------------------ 16c. Documentation ------------------------------------------------------------------------ 17. Demo Code A full list of demonstration code can be found in the file Òapplications.infoÓ which is found on the BBS and the FTP site. ------------------------------------------------------------------------ 18. Application Notes The following is a list of all current application notes not included in the manual. A full list of applications notes can be found in the file Òapplications.infoÓ which is found on the BBS and the FTP site.