This file contains customization area code for all production versions
of the 340Bug debug monitor.  Note that the checksum shown for each
revision reflects changes in other parts of the monitor in addition to
the customization area.

Last modified: 9/14/92 BH

*********************************************************************
* 340Bug Revision 1.01 customization area
*
BUG101   ORG  $00060000
*
PWR_SSP  DC.L $00002FFC    POR stack pointer
PWR_PC   DC.L $00060090    POR program counter
CODESIZE DC.L $00020000    Size of 340Bug ROM in bytes
CHECKALT DC.W $FFFF        Checksum alternate
CHECKSUM DC.W $C9EB        Checksum
FILL1    DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF,$FFFFFFFF
         DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF,$FFFFFFFF
         DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF,$FFFFFFFF
CSAM0    DC.L $0001FFFD    CS0 Address mask register
CSBAR0   DC.L $0007FFF9        Base address register
CSAM1    DC.L $0000FFF1    CS1 Address mask register
CSBAR1   DC.L $0000FFF5        Base address register
CSAM2    DC.L $000007F1    CS2 Address mask register
CSBAR2   DC.L $00FFEFF1        Base address register
CSAM3    DC.L $0000FFFD    CS3 Address mask register
CSBAR3   DC.L $0001FFF1        Base address register
FILL2    DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF
RESERVED DC.L $FFFFFFFF    Reserved
FILL3    DC.L $FFFFFFFF





*********************************************************************
* 340Bug Revision 1.02 customization area
* An "*" at the end of a line indicates changed from rev 1.01
*
BUG102   ORG  $00060000
*
PWR_SSP  DC.L $00002FFC    POR stack pointer
PWR_PC   DC.L $00060090    POR program counter
CODESIZE DC.L $00020000    Size of 340Bug ROM in bytes
CHECKALT DC.W $FFFF        Checksum alternate
CHECKSUM DC.W $1614        Checksum                   *
FILL1    DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF,$FFFFFFFF
         DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF,$FFFFFFFF
         DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF,$FFFFFFFF
CSAM0    DC.L $0001FFFD    CS0 Address mask register
CSBAR0   DC.L $0007FFF9        Base address register
CSAM1    DC.L $0000FFF1    CS1 Address mask register
CSBAR1   DC.L $0000FFF5        Base address register
CSAM2    DC.L $000007F1    CS2 Address mask register
CSBAR2   DC.L $00FFEFF1        Base address register
CSAM3    DC.L $0003FFFD    CS3 Address mask register  *
CSBAR3   DC.L $0003FFF1        Base address register  *
FILL2    DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF
RESERVED DC.L $FFFFFFFF    Reserved
FILL3    DC.L $FFFFFFFF





*********************************************************************
* 340Bug Revision 1.03 customization area - PRELIMINARY
* Includes the following changes:
*   1) Base address bits which are masked by the corresponding address
*      mask register bit are changed to zero for clarity.  The resulting
*      value more closely matches the actual starting address of the
*      address range defined.
*   2) NCS (no CPU space) bit is set in each base address register to
*      prevent the chip select from responding to CPU space accesses.
*      This bit was added with the 1D76F/rev D 68340 mask set - attempts
*      to set this bit are ignored on 1C67H/rev A and D45C/rev B silicon.
*
* An "*" at the end of a line indicates changed from rev 1.02
*
BUG103P  ORG  $00060000
*
PWR_SSP  DC.L $00002FFC    POR stack pointer
PWR_PC   DC.L $00060090    POR program counter
CODESIZE DC.L $00020000    Size of 340Bug ROM in bytes
CHECKALT DC.W $FFFF        Checksum alternate
CHECKSUM DC.W $21CE        Checksum                   *
FILL1    DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF,$FFFFFFFF
         DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF,$FFFFFFFF
         DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF,$FFFFFFFF
CSAM0    DC.L $0001FFFD    CS0 Address mask register
CSBAR0   DC.L $0006000B        Base address register  *
CSAM1    DC.L $0000FFF1    CS1 Address mask register
CSBAR1   DC.L $00000007        Base address register  *
CSAM2    DC.L $000000F3    CS2 Address mask register
CSBAR2   DC.L $00FFE803        Base address register  *
CSAM3    DC.L $0003FFFD    CS3 Address mask register
CSBAR3   DC.L $00000003        Base address register  *
FILL2    DC.L $FFFFFFFF,$FFFFFFFF,$FFFFFFFF
RESERVED DC.L $FFFFFFFF    Reserved
FILL3    DC.L $FFFFFFFF