This files contains the assembly code routines from the MC68340 User's Manual,
document number MC68340UM/AD Rev. 1.


1. SIM40 Example Configuration Code
The following code is an example configuration sequence for the SIM40 module.
***************************************************************************
* MC68340 basic SIM40 register initialization example code:
* This code is used to initialize the 68340's internal SIM40 registers,
* providing basic functions for operation.
* It includes chip select programming for external devices.
* This code would be programmed beginning at offset $0 into ROM which is
* relocated to address $60000 by the initialization code.
* The SSP_VEC and RST_VEC vectors used to initialize the system stack
* pointer and initial PC, respectively, are located at offset $0 after
* reset.
***************************************************************************
* equates
***************************************************************************
SSP_INIT EQU	$10000		Stack pointer initial value - top of RAM
MBAR	EQU	$0003FF00	Address of Module Base Address Reg.
MODBASE	EQU	$FFFFF100	Default Module Base address value

****************************************
* SIM40 register offsets from MBAR base address
MCR	EQU	$00
SYNCR	EQU	$04
SYPCR	EQU	$21
CSAM0	EQU	$40
CSBAR0	EQU	$44
CSAM1	EQU	$48
CSBAR1	EQU	$4c
CSAM2	EQU	$50
CSBAR2	EQU	$54
CSAM3	EQU	$58
CSBAR3	EQU	$5c
***************************************************************************
* Reset vectors
* These two vectors should be located at addresses $0 and $4 after a processor
* hardware reset.
***************************************************************************
	ORG	$60000
SSP_VEC	DC.L	SSP_INIT	Supervisor stack pointer - initial value
RST_VEC	DC.L	INIT340		Reset vector pointing to initialization code

***************************************************************************
* Initialization code
***************************************************************************

* Start Chip Select Initialization:
INIT340	MOVE.W	#$2700,SR		Init SR - interrupts masked

***************************************************************************
* Set up default module base address value
	MOVEQ.L	#7,D0			MBAR is in CPU space
	MOVEC.L	D0,DFC			load DFC to indicate CPU space
	MOVE.L	#MODBASE+1,D0		Set address/valid bit
	MOVES.L	D0,MBAR			write to MBAR

***************************************************************************
* Set up system protection register:
* Software watchdog disabled, double bus fault monitor disabled, bus
* monitor BERR after 16 clocks.
	MOVE.B	#6,SYPCR+MODBASE

***************************************************************************
* Clock synthesizer control register:
* Switch from 8.3 to 16.7 MHZ
	MOVE.W	#$7F00,SYNCR+MODBASE	X-bit doubles the default speed

***************************************************************************
* Module configuration register:
* When FREEZE is asserted, software watchdog and periodic interrupt timer
* are disabled, bus monitor is enabled.  Port B = 4 IRQs, 4 chip selects.
* Show Cycles enabled, external arbitration enabled. Supervisor/user
* SIM registers unrestricted, Interrupt Arbitration at priority $F
	MOVE.W	#$420F,MCR+MODBASE

***************************************************************************
* Now, set up Address masks and base addresses for the chip selects:
	LEA       CSAM0+MODBASE,A0	Point to CS0 addr. mask location.
	MOVEQ     #7,D0			Set up a loop counter.
	LEA       CSAM0$,A1		Point to addr mask memory location.
LOOP    MOVE.L    (A1)+,(A0)+		Init. addr mask and base addr reg
	DBRA      D0,LOOP

***************************************************************************
*  Data table for chip select initialization
***************************************************************************

* CS0 - EPROM - 00060000-0007ffff, 3-wait states, 16-bit term., write protect
CSAM0$	DC.L	$0001FFFD
CSBAR0$	DC.L	$00060009
* CS1 - RAM - 00000000-0000ffff, fast termination
CSAM1$	DC.L	$0000FFF0
CSBAR1$	DC.L	$00000005
* CS2 - external device - 00FFE8xx, external termination
CSAM2$	DC.L	$000000F3
CSBAR2$	DC.L	$00FFE801
* CS3 - secondary memory - 00000000-0003ffff, 3-wait states, 16-bit term.
CSAM3$	DC.L	$0003FFFD
CSBAR3$	DC.L	$00000001

	END
***************************************************************************

2. DMA Channel Example Configuration Code
The following are examples of configuration sequences for a DMA channel in single- and dual-addressing modes.
Example 1: External Burst Request Generation, Single-Address Transfers.
***************************************************************************
* MC68340 basic DMA channel register initialization example code.
* This code is used to initialize the 68340's internal DMA channel 
* registers, providing basic functions for operation.
* The code sets up channel 1 for external burst request generation, 
* single-address mode, long word size transfers.
* Control signals are asserted on the DMA read cycle. 
***************************************************************************
***************************************************************************
* SIM40 equates
***************************************************************************
MBAR	EQU	$0003FF00	Address of SIM40 Module Base Address Reg.
MODBASE	EQU	$FFFFF100	SIM40 MBAR address value

****************************************
***********************
* DMA Channel 1 equates
DMACH1	EQU	$780		Offset from MBAR for channel 1 regs
DMAMCR1	EQU	$0		MCR for channel 1

* Channel 1 register offsets from channel 1 base address
DMAINT1	EQU	$4		interrupt register channel 1
DMACCR1	EQU	$8		control register channel 1
DMACSR1	EQU	$A		status register channel 1
DMAFCR1	EQU	$B		function code register channel 1
DMASAR1	EQU	$C		source address register channel 1
DMADAR1	EQU	$10		destination address register channel 1
DMABTC1	EQU	$14		byte transfer count register channel 1
SARADD	EQU	$10000		source address
NUMBYTE	EQU	$C		number of bytes to transfer

***************************************************************************
***************************************************************************
* Initialize DMA Channel 1 
***************************************************************************
	LEA	MODBASE+DMACH1,A0	Pointer to channel 1 

* Initialize DMA channel 1 MCR
* Normal Operation, ignore FREEZE, single-address mode. ISM field at 2. Make 
* sure CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel startup.
* Supervisor/user reg. unrestricted, MAID field at 7. IARB priority at 1.
	MOVE.W	#$1271,(A0)

* Clear channel control reg.
* Clear STR (start) bit to prevent the channel from starting a transfer early.
	CLR.W	DMACCR1(A0)

* Initialize interrupt reg.
* Interrupt priority at 7, interrupt vector at $42.
	MOVE.W	#$0742,DMAINT1(A0)

* Initialize channel status reg.
* Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup.
	MOVE.B	#$7C,DMACSR1(A0)

* Initialize function code reg.
* DMA space, user data space for source.
	MOVE.B	#$99,DMAFCR1(A0)

* Initialize source operand address 
* Source address is equal to $10000.
	MOVE.L	SARADD,DMASAR1(A0)

* Initialize the byte transfer count reg.
* The number of bytes to be transferred is $C or 3 long words
	MOVE.L	NUMBYTE,DMABTC1(A0)

* Channel control reg. init. and Start DMA transfers
* No interrupts are enabled, source (read) cycle. Increment source 
* address, source size is long word, REQ is external burst request.
* Single-address mode, start the DMA transfers.
	MOVE.W	#$1823,DMACCR1(A0)

***************************************************************************
	END
***************************************************************************

Example 2: Internal Request Generation, Memory to Memory Transfers.
***************************************************************************
* MC68340 basic DMA channel register initialization example code.
* This code is used to initialize the 68340's internal DMA channel 
* registers, providing basic functions for operation.
* The code sets up channel 1 for internal request generation 
* memory to memory transfers. 
***************************************************************************
***************************************************************************
* SIM40 equates
***************************************************************************
MBAR	EQU	$0003FF00	Address of SIM40 Module Base Address Reg.
MODBASE	EQU	$FFFFF100	SIM40 MBAR address value

****************************************
***********************
* DMA Channel 1 equates
DMACH1	EQU	$780		Offset from MBAR for channel 1 regs
DMAMCR1	EQU	$0		MCR for channel 1

* Channel 1 register offsets from channel 1 base address
DMAINT1	EQU	$4		interrupt register channel 1
DMACCR1	EQU	$8		control register channel 1
DMACSR1	EQU	$A		status register channel 1
DMAFCR1	EQU	$B		function code register channel 1
DMASAR1	EQU	$C		source address register channel 1
DMADAR1	EQU	$10		destination address register channel 1
DMABTC1	EQU	$14		byte transfer count register channel 1
SARADD	EQU	$6000		source address
DARADD	EQU	$8000		destination address
NUMBYTE	EQU	$E		number of bytes to transfer

***************************************************************************
***************************************************************************
* Initialize DMA Channel 1 
***************************************************************************
	LEA	MODBASE+DMACH1,A0	Pointer to channel 1 

* Initialize DMA channel 1 MCR
* Normal Operation, ignore FREEZE, dual-address mode. ISM field at 3. Make 
* sure CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel startup.
* Supervisor/user reg. unrestricted, MAID field at 3. IARB priority at 4.
	MOVE.W	#$0334,(A0)

* Clear channel control reg.
* Clear STR (start) bit to prevent the channel from starting a transfer early.
	CLR.W	DMACCR1(A0)

* Initialize interrupt reg.
* Interrupt priority at 7, interrupt vector at $42.
	MOVE.W	#$0742,DMAINT1(A0)

* Initialize channel status reg.
* Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup.
	MOVE.B	#$7C,DMACSR1(A0)

* Initialize function code reg.
* DMA space, supervisor data space for source and destination.
	MOVE.B	#$DD,DMAFCR1(A0)

* Initialize source operand address 
* Source address is equal to $6000.
	MOVE.L	SARADD,DMASAR1(A0)

* Initialize destination operand address
* Destination address is equal to $8000.
	MOVE.L	DARADD,DMADAR1(A0)

* Initialize the byte transfer count reg.
* The number of bytes to be transferred is $E or 7 words
	MOVE.L	NUMBYTE,DMABTC1(A0)

* Channel control reg. init. and Start DMA transfers
* No interrupts are enabled, destination (write) cycle. Increment source and
* destination addresses,source size is word, destination size is word.
* REQ is internal. 100% of bus bandwidth, dual-address transfers,
* start the DMA transfers.
	MOVE.W	#$0E8D,DMACCR1(A0)

***************************************************************************
	END
***************************************************************************

Example 3: Internal Request Generation, Memory Block Initialization.
***************************************************************************
* MC68340 basic DMA channel register initialization example code.
* This code is used to initialize the 68340's internal DMA channel 
* registers, providing basic functions for operation.
* The code sets up channel 1 for internal request generation 
* to perform a memory block initialization for 100 bytes. 
***************************************************************************
***************************************************************************
* SIM40 equates
***************************************************************************
MBAR	EQU	$0003FF00	Address of SIM40 Module Base Address Reg.
MODBASE	EQU	$FFFFF100	SIM40 MBAR address value

****************************************
***********************
* DMA Channel 1 equates
DMACH1	EQU	$780		Offset from MBAR for channel 1 regs
DMAMCR1	EQU	$0		MCR for channel 1

* Channel 1 register offsets from channel 1 base address
DMAINT1	EQU	$4		interrupt register channel 1
DMACCR1	EQU	$8		control register channel 1
DMACSR1	EQU	$A		status register channel 1
DMAFCR1	EQU	$B		function code register channel 1
DMASAR1	EQU	$C		source address register channel 1
DMADAR1	EQU	$10		destination address register channel 1
DMABTC1	EQU	$14		byte transfer count register channel 1
SARADD	EQU	$6000		source address
DARADD	EQU	$8000		destination address
NUMBYTE	EQU	$64		number of bytes to transfer

***************************************************************************
***************************************************************************
* Initialize DMA Channel 1 
***************************************************************************
	LEA	MODBASE+DMACH1,A0	Pointer to channel 1 

* Initialize DMA channel 1 MCR
* Normal Operation, ignore FREEZE, dual-address mode. ISM field at 3. Make 
* sure CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel 
* startup.Supervisor/user reg. unrestricted, MAID field at 3.
* IARB priority at 4.
	MOVE.W	#$0334,(A0)

* Clear channel control reg.
* Clear STR (start) bit to prevent the channel from starting a transfer early.
	CLR.W	DMACCR1(A0)

* Initialize interrupt reg.
* Interrupt priority at 7, interrupt vector at $42.
	MOVE.W	#$0742,DMAINT1(A0)

* Initialize channel status reg.
* Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup.
	MOVE.B	#$7C,DMACSR1(A0)

* Initialize function code reg.
* DMA space, supervisor data space for source and destination.
	MOVE.B	#$DD,DMAFCR1(A0)

* Initialize source operand address 
* Source address is equal to $6000.
	MOVE.L	SARADD,DMASAR1(A0)

* Initialize destination operand address
* Destination address is equal to $8000.
	MOVE.L	DARADD,DMADAR1(A0)

* Initialize the byte transfer count register
* The number of bytes to be transferred is $64 or 50 words
	MOVE.L	NUMBYTE,DMABTC1(A0)

* Channel control reg. init. and Start DMA transfers
* No interrupts are enabled, destination (write) cycle.
* Source address is not incremented. Increment the destination address.
* Source size is word, destination size is word. REQ is internal. 
* 100% of bus bandwidth, dual-address transfers, start the DMA transfers.
	MOVE.W	#$068D,DMACCR1(A0)

***************************************************************************
	END
***************************************************************************

Example 4: Cycle Steal Request Generation, Dual-Address Transfers.
***************************************************************************
* MC68340 basic DMA channel register initialization example code.
* This code is used to initialize the 68340's internal DMA channel 
* registers, providing basic functions for operation.
* The code sets up channel 1 for external cycle steal request generation, 
* dual-address transfers. DMA 16-bit wide data from an odd address to an 
* even address. Control signals are asserted on the DMA read cycle. 
***************************************************************************
***************************************************************************
* SIM40 equates
***************************************************************************
MBAR	EQU	$0003FF00	Address of SIM40 Module Base Address Reg.
MODBASE	EQU	$FFFFF100	SIM40 MBAR address value

****************************************
***********************
* DMA Channel 1 equates
DMACH1	EQU	$780		Offset from MBAR for channel 1 regs
DMAMCR1	EQU	$0		MCR for channel 1

* Channel 1 register offsets from channel 1 base address
DMAINT1	EQU	$4		interrupt register channel 1
DMACCR1	EQU	$8		control register channel 1
DMACSR1	EQU	$A		status register channel 1
DMAFCR1	EQU	$B		function code register channel 1
DMASAR1	EQU	$C		source address register channel 1
DMADAR1	EQU	$10		destination address register channel 1
DMABTC1	EQU	$14		byte transfer count register channel 1
SARADD	EQU	$6001		source address is an ODD address
DARADD	EQU	$10000		destination address is and EVEN address
NUMBYTE	EQU	$14		number of bytes to transfer

***************************************************************************
***************************************************************************
* Initialize DMA Channel 1 
***************************************************************************
	LEA	MODBASE+DMACH1,A0	Pointer to channel 1 

* Initialize DMA channel 1 MCR
* Normal Operation, ignore FREEZE, dual-address mode. ISM field at 0. Make 
* CPU32 SR I2-I0 bits are less than or equal to ISM bits for channel startup.
* Supervisor/user reg. unrestricted, MAID field at 4. IARB priority at 8.
	MOVE.W	#$00C8,(A0)

* Clear channel control reg.
* Clear STR (start) bit to prevent the channel from starting a transfer early.
	CLR.W	DMACCR1(A0)

* Initialize interrupt reg.
* Interrupt priority at 7, interrupt vector at $42.
	MOVE.W	#$0742,DMAINT1(A0)

* Initialize channel status reg.
* Clear the DONE, BES, BED, CONF and BRKP bits to allow channel to startup.
	MOVE.B	#$7C,DMACSR1(A0)

* Initialize function code reg.
* DMA space, supervisor data space for source and destination.
	MOVE.B	#$DD,DMAFCR1(A0)

* Initialize source operand address 
* Source address is equal to $6001, and odd address.
	MOVE.L	SARADD,DMASAR1(A0)

* Initialize destination operand address
* Destination address is equal to $10000, and even address.
	MOVE.L	DARADD,DMADAR1(A0)

* Initialize the byte transfer count register
* The number of bytes to be transferred is $14 or 20 bytes
	MOVE.L	NUMBYTE,DMABTC1(A0)

* Channel control reg. init. and Start DMA transfers
* No interrupts are enabled, source (read) cycle.
* Increment the source and destination addresses.
* Source size is byte, destination size is word. REQ is external cycle steal. 
* dual-address transfers, start the DMA transfers.
	MOVE.W	#$1DB1,DMACCR1(A0)

***************************************************************************
	END
***************************************************************************


3. Serial Module Example Configuration Code
The following code is an example of a configuration sequence for the serial module.
***************************************************************************
* MC68340 basic serial module register initialization example code.
* This code is used to initialize the 68340's internal serial module registers,
* providing basic functions for operation.
* It sets up serial channel A for communication with a 9600 baud terminal. 
* Note: All serial module registers must be accessed as bytes.
***************************************************************************
***************************************************************************
* equates
***************************************************************************
MBAR	EQU	$0003FF00	Address of SIM40 Module Base Address Reg.
MODBASE	EQU	$FFFFF100	SIM40 MBAR address value

****************************************
***********************
* Serial module equates
SERIAL	EQU	$700		Offset from MBAR for serial module regs
MCRH	EQU	$0		serial MCR high byte
MCRL	EQU	$1		serial MCR low byte

* Serial register offsets from serial base address
MR1A	EQU	$10		Mode register 1 A
MR2A	EQU	$20		Mode register 2 A
SRA	EQU	$11		Status register A
CSRA	EQU	$11		Clock select reg A
CRA	EQU	$12		Command reg A

ACR	EQU	$14		Auxillary control reg
OPCR	EQU	$1D		Output port control reg
OP_BS	EQU	$1E		Output port bit set (write 1 to set)
OP_BR	EQU	$1F		Output port bit reset (write 1 to clear)


***************************************************************************
***************************************************************************
* Initialize Serial channel A 
***************************************************************************
	LEA	MODBASE+SERIAL,A0	Pointer to serial channel A

* Module configuration register:
* Enable serial module for normal operation, ignore FREEZE, select the 
* crystal clock. Supervisor/user serial registers unrestricted.
* Interrupt arbitration at priority $02.
	MOVE.B	#$00,MCRH(A0)
	MOVE.B	#$02,MCRL(A0)

* WAIT FOR TRANSMITTER EMPTY (OR TIMEOUT)
	MOVE.W	#$2000,D0		init loop counter
XBMTWAIT EQU	*
	BTST	#3,SRA(A0)		TX empty in status reg?
	NOP
	DBNE	D0,XBMTWAIT		loop until set or timeout

* NEGATE RTSA SIGNAL OUTPUT
	MOVE.B	#0,OPCR(A0)		make OP0-7 general purpose
	MOVE.B	#$01,OP_BR(A0)		clear RTSA/OP0 output

* RESET RECEIVER/TRANSMITTER
	MOVE.B	#$20,CRA(A0)		Issue reset receiver command
	MOVE.B	#$30,CRA(A0)		Issue reset transmitter command

* SET BAUD RATE SET 2
	MOVE.B	#$80,ACR(A0)

* MODE REGISTER 1
	MOVE.B	#$93,MR1A(A0)		8 bits, no parity, auto RTS control

* MODE REGISTER 2
	MOVE.B	#$07,MR2A(A0)		Normal, 1 stop bit

* SET UP BAUD RATE FOR PORT IN CLOCK SELECT REGISTER
	MOVE.B	#$BB,CSRA(A0)		Set 9600 baud for RX and TX

* SET RTSA ACTIVE
	MOVE.B	#$01,OP_BS(A0)		set RTSA/OP0 output

* ENABLE PORT
	MOVE.B	#$45,CRA(A0)		Reset error status, enable RX & TX

***************************************************************************
	END
***************************************************************************

4. Timer Module Example Configuration Code
The following code is an example of a configuration sequence for the timer module.
***************************************************************************
* MC68340 basic timer module register initialization example code.
* This code is used to initialize the 68340's internal timer module 
* registers, providing basic functions for operation.
* It sets up timer1 for square wave generation. 
***************************************************************************
***************************************************************************
* equates
***************************************************************************
MBAR	EQU	$0003FF00	Address of SIM40 Module Base Address Reg.
MODBASE	EQU	$FFFFF100	SIM40 MBAR address value

****************************************
***********************
* Timer1 module equates
TIMER1	EQU	$600		Offset from MBAR for timer1 module regs
MCR1	EQU	$0		MCR for timer1

* Timer1 register offsets from timer1 base address
IR1	EQU	$04		interrupt register timer1
CR1	EQU	$06		command register timer1
SR1	EQU	$08		status register timer1
CNTR1	EQU	$0A		counter register timer1
PRLD11	EQU	$0C		preload register 1 timer1
COM1	EQU	$10		compare register timer1


***************************************************************************
***************************************************************************
* Initialize Timer1 
***************************************************************************
	LEA	MODBASE+TIMER1,A0	Pointer to timer1 module

* Disable timer1
	CLR.W	CR1(A0)

* Clear the TO, TG, and TC bits
	CLR.W	SR1(A0)

* Module configuration register:
* Timer1 module is set for normal operation, ignore FREEZE.
* Supervisor/user timer1 registers unrestricted.
* Interrupt arbitration at priority $03.
	MOVE.W	#$0003,MCR1(A0)

* Initialize timer1 interrupt level to 2 and vector to $0F
	MOVE.W	#$020F,IR1(A0)

* Initialize preload 1 to 3
	MOVE.W	#$0003,PRLD11(A0)


* Initialize the compare register to 0
	CLR.W	COM1(A0)

* Command register 1:
* Enable timer1, no interrupts are enabled, TGATE signal has no effect.
* Use the selected clock for the counter clock, and enable it.
* Selected clock is 1/2 system's freq.. Square-wave generation, toggle TOUT.
	MOVE.W	#$8205,CR1(A0)
***************************************************************************
	END
***************************************************************************


***************************************************************************
* MC68340 basic timer module register initialization example code.
* This code is used to initialize the 68340's internal timer module 
* registers, providing basic functions for operation.
* It sets up timer1 for pulse-width measurement. In this mode, the number
* of clock cycles during a particular event are counted. The event is
* defined by the assertion and negation of TGATE.
***************************************************************************
***************************************************************************
* equates
***************************************************************************
MBAR	EQU	$0003FF00	Address of SIM40 Module Base Address Reg.
MODBASE	EQU	$FFFFF100	SIM40 MBAR address value

****************************************
***********************
* Timer1 module equates
TIMER1	EQU	$600		Offset from MBAR for timer1 module regs
MCR1	EQU	$0		MCR for timer1

* Timer1 register offsets from timer1 base address
IR1	EQU	$04		interrupt register timer1
CR1	EQU	$06		command register timer1
SR1	EQU	$08		status register timer1
CNTR1	EQU	$0A		counter register timer1
COM1	EQU	$10		compare register timer1


***************************************************************************
***************************************************************************
* Initialize Timer1 
***************************************************************************
	LEA	MODBASE+TIMER1,A0	Pointer to timer1 module

* Disable timer1
	CLR.W	CR1(A0)

* Allow TGATE to negate and assert so that an accurate count will result.
* If SR1 TGL bit=1, continue looping. TGATE is negated.
  LOOP1	BTST.B 	#$3,SR1(A0)
	BNE.B	LOOP1
* If TGL bit=0, continue looping. TGATE is asserted.
  LOOP2	BTST.B 	#$3,SR1(A0)
	BEQ.B	LOOP2

* Ready to initialize timer1, TGATE is negated.

* Module configuration register:
* Timer1 module is set for normal operation, ignore FREEZE.
* Supervisor/user timer1 registers unrestricted.
* Interrupt arbitration at priority $03.
	MOVE.W	#$0003,MCR1(A0)

* Initialize timer1 interrupt level to 2 and vector to $0F
	MOVE.W	#$020F,IR1(A0)

* Initialize the compare register to 0
	CLR.W	COM1(A0)

* Clear the SR1 TG bit (by writing a 1) to use as a flag
	MOVE.B	#$20,SR1(A0)

* Command register 1:
* Enable timer1, no interrupts are enabled, TGATE signal used to control
* the counter. Use the selected clock for the counter clock, and enable it.
* Selected clock is 1/2 system's freq.. Pulse-width measurement,
* disable TOUT.
	MOVE.W	#$8A10,CR1(A0)

* If SR TG bit=0, continue looping TGATE is asserted,
* else TG=1 indicating TGATE was negated. When TG=1, counting is stopped.
  LOOP3	BTST.B	#$5,SR1(A0)
	BEQ.B	LOOP3

* Counting is complete. To determine the number of cycles counted, the value
* in CNTR1 must be read, inverted, and incremented by 1.
	MOVE.W	CNTR1(A0),D0
	NOT.W	D0
	ADDQ.W	#$1,DO
* D0 contains the number of cycles counted.
***************************************************************************
	END
***************************************************************************