********************************************************* * Ethernet Programming Example Using Interrupts * * * * This code is derived from the Ethernet sample code on * * page 7-272 of the 68360 User's Manual but uses 4 * * transmit and 4 receive BDs along with an interrupt * * driven receive routine * * * * *** Note **** * * This code will NOT work on the QUADS board because * * the Ethernet port is hooked to the slave QUICC on * * the QUADS board. In order to use the Ethernet port * * on the QUADS board, use The file "esl_ex" instead. * * * JS 7/14/94 * ********************************************************* * Revision History * 7/14/94 Original Revision * 11/10/94 Fixed to work with the EEST ********************************************************* * 1) The code sets up SCC1 in Ethernet mode * * 2) It sets up 4 transmit buffer descriptors that * * that will send data when the transmitter is enabled. * * 3) It sets up 4 receive buffer descriptors to receive * * the incoming data * * 4) It sets up the vectors to the interrupt handling * * routines * * 5) Finally, it turns on the transmitter and receiver * * in normal mode * ********************************************************* * If you wish to move this code so that it works on * * another SCC, there are quite a few things that need to* * be done. * * 1) Change the names of all of the SCC equates * * 2) Change the SCC1PB equate to SCCx and set it * * to the correct offset (see page 3-4) * * 3) Change the equate for the SCC Vector * * 4) Change the port pin setup instructions so * * that they activate the correct pins * * 5) Change the SICR register so that the correct * * SCC gets clocking * * 6) Change the INIT RX&TX PARAMETERS command so * * that it refers to the correct SCC (p. 7-7) * * 7) Change the CIMR setup so that the new SCC * * can generate interrupts * * 8) Change the CISR clearing in the interrupt * * service routine so that it clears the bit * * corresponding to the new SCC * *********************************************************************** ************************************************************* * INIT EQU $0405000 ; QUADS Board DRAM User Space * ************************** DUAL PORT RAM MBAR EQU $03FF00 ; Module Base Address, (MBAR)=REGB MBARE EQU $03FF08 ; Module Base Address Enable SLAVE * *********************************************************************** * The following equates assume that they will be used in register * indirect addressing. The address register should hold the base * address of the QUICC internal memory. All system equates are * offsets into this memory REGB EQU $1000 ; Base address of Internal Registers SCC1PB EQU $0C00 ; SCC1 Protocol Base address ************************ SIM Module registers MCR EQU REGB+$0000 ; Module Configuration AVR EQU REGB+$0008 ; Auto Vector RSR EQU REGB+$0009 ; Reset Status CLKOCR EQU REGB+$000C ; CLKO Control PPLCR EQU REGB+$0010 ; PPL Control CDVCR EQU REGB+$0014 ; Clock Divider Control * PEPAR EQU REGB+$0016 ; Port E Pin Assignment * SYPCR EQU REGB+$0022 ; System Protection Control SWIV EQU REGB+$0023 ; S/w Interrupt Vector PICR EQU REGB+$0026 ; Periodic Interrupt Control PITR EQU REGB+$002A ; Periodic Interrupt Timing SWSR EQU REGB+$002F ; S/w Service BKAR EQU REGB+$0032 ; Breakpoint Address BKCQ EQU REGB+$0034 ; Breakpoint Control * * ************************ CPM Module registers ******************* * ICCR EQU REGB+$0500 ; Channel Configuration *** SDMA SDSR EQU REGB+$051C ; SDMA Status SDCR EQU REGB+$051E ; SDMA Configuration Register SDAR EQU REGB+$0520 ; SDMA Address Register *** CP Interrupt CICR EQU REGB+$0540 ; CP Interrupt Configuration CIPR EQU REGB+$0544 ; CP Interrupt Pending CIMR EQU REGB+$0548 ; CP Interrupt Mask CISR EQU REGB+$054C ; CP Interrupt In-service *** Port A, B, C PADIR EQU REGB+$0550 ; Port A Data Direction Assignment PAPAR EQU REGB+$0552 ; Port A Pin Function Assignment PAODR EQU REGB+$0554 ; Port A Open Drain Assignment PADAT EQU REGB+$0556 ; Port A Data Content * PBDIR EQU REGB+$06B8 ; Port B Data Direction Assignment PBPAR EQU REGB+$06BC ; Port B Pin Function Assignment PBODR EQU REGB+$06C0 ; Port B Open Drain Assignment PBDAT EQU REGB+$06C4 ; Port B Data Content * PCDIR EQU REGB+$0560 ; Port C Data Direction Assignment PCPAR EQU REGB+$0562 ; Port C Pin Assignment PCSO EQU REGB+$0564 ; Port C Special Options PCDAT EQU REGB+$0566 ; Port C Data Content PCINT EQU REGB+$0568 ; Port C Interrupt Control *** CP CR EQU REGB+$05C0 ; CP Command RCCR EQU REGB+$05C4 ; RISC Configuration RTER EQU REGB+$05D6 ; RISC Timer Event Register RTMR EQU REGB+$05DA ; RISC Timer Mask Register * BRG 1, 2, 3, 4 BRGC1 EQU REGB+$05F0 ; BRG1 Configuration BRGC2 EQU REGB+$05F4 ; BRG2 Configuration BRGC3 EQU REGB+$05F8 ; BRG3 Configuration BRGC4 EQU REGB+$05FC ; BRG4 Configuration *** SCC 1, 2, 3, 4 * SCC1 GSMR_L1 EQU REGB+$0600 ; SCC1 General Mode GSMR_H1 EQU REGB+$0604 ; SCC1 General Mode PSMR1 EQU REGB+$0608 ; SCC1 Protocol Specific Mode TODR1 EQU REGB+$060C ; SCC1 Transmit On Demand DSR1 EQU REGB+$060E ; SCC1 Data Sync SCCE1 EQU REGB+$0610 ; SCC1 Event SCCM1 EQU REGB+$0614 ; SCC1 Mask SCCS1 EQU REGB+$0617 ; SCC1 Status *** Serial Interface SIMODE EQU REGB+$06E0 ; SI Mode SIGMR EQU REGB+$06E4 ; SI Global Mode SISTR EQU REGB+$06E6 ; SI Status SICMR EQU REGB+$06E7 ; SI Command SICR EQU REGB+$06EC ; SI Clock Routing SIRP EQU REGB+$06F0 ; SI RAM Pointer SIRAM EQU REGB+$0700 ; SI Routing RAM ************************ END of SIM/CPM Register MAP ************************ SCC Parameters ****** SCC1 RBASE1 EQU SCC1PB+$000 ; SCC1 RX BD Base Address TBASE1 EQU SCC1PB+$002 ; SCC1 TX BD Base Address RFCR1 EQU SCC1PB+$004 ; SCC1 RX Function Code TFCR1 EQU SCC1PB+$005 ; SCC1 TX Function Code MRBLR1 EQU SCC1PB+$006 ; SCC1 MAX Buffer Length - RX RSTATE1 EQU SCC1PB+$008 ; SCC1 RX Internal State RBPRT1 EQU SCC1PB+$010 ; SCC1 RX BD Pointer TSTATE1 EQU SCC1PB+$018 ; SCC1 TX Internal State TBPRT1 EQU SCC1PB+$020 ; SCC1 TX BD Pointer RCRC1 EQU SCC1PB+$028 ; SCC1 Temp Receive CRC TCRC1 EQU SCC1PB+$02C ; SCC1 Temp Transmit CRC ************************** Specific Parameters * SCC1, Ethernet Specific Parameter C_PRES1 EQU SCC1PB+$30 ; SCC1 Preset CRC ($FFFFFFFF) C_MASK1 EQU SCC1PB+$34 ; SCC1 Constant mask for CRC($20E3DEBB) CRCEC1 EQU SCC1PB+$38 ; SCC1 CRC error counter ALEC1 EQU SCC1PB+$3C ; SCC1 alignment error counter DISFC1 EQU SCC1PB+$40 ; SCC1 discard frame counter PADS1 EQU SCC1PB+$44 ; SCC1 short frame PAD counter RET_Lim1 EQU SCC1PB+$46 ; SCC1 retry limit threshold RET_cnt1 EQU SCC1PB+$48 ; SCC1 retry limit counter MFLR1 EQU SCC1PB+$4A ; SCC1 max. frame length reg. MINFLR1 EQU SCC1PB+$4C ; SCC1 min. frame length reg. MAXD11 EQU SCC1PB+$4E ; SCC1 max. DMA1 length reg. MAXD21 EQU SCC1PB+$50 ; SCC1 max. DMA2 length reg. MAXD1 EQU SCC1PB+$52 ; SCC1 Rx max DMA DMA_cnt1 EQU SCC1PB+$54 ; SCC1 Rx DMA count MAX_b1 EQU SCC1PB+$56 ; SCC1 max BD byte count GADDR11 EQU SCC1PB+$58 ; SCC1 Group Addr. Filter 1 GADDR21 EQU SCC1PB+$5A ; SCC1 Group Addr. Filter 2 GADDR31 EQU SCC1PB+$5C ; SCC1 Group Addr. Filter 3 GADDR41 EQU SCC1PB+$5E ; SCC1 Group Addr. Filter 4 TBUF0.data01 EQU SCC1PB+$60 ; SCC1 save area 0 - current frame TBUF0.data11 EQU SCC1PB+$64 ; SCC1 save area 1 - current frame TBUF0.rba01 EQU SCC1PB+$68 ; SCC1 TBUF0.crc1 EQU SCC1PB+$6C ; SCC1 TBUF0.bcnt1 EQU SCC1PB+$70 ; SCC1 PADDR1_H1 EQU SCC1PB+$72 ; physical address 1 (MSB) PADDR1_M1 EQU SCC1PB+$74 ; physical address 1 PADDR1_L1 EQU SCC1PB+$76 ; physical address 1 (LSB) P_PER1 EQU SCC1PB+$78 ; persistence RFBD_ptr1 EQU SCC1PB+$7A ; Rx first BD pointer TFBD_ptr1 EQU SCC1PB+$7C ; Tx first BD pointer TLBD_ptr1 EQU SCC1PB+$7E ; Tx last BD pointer TBUF1.data01 EQU SCC1PB+$80 ; SCC1 save area 0 - next frame TBUF1.data11 EQU SCC1PB+$84 ; SCC1 save area 1 - next frame TBUF1.rba01 EQU SCC1PB+$88 ; SCC1 TBUF1.crc1 EQU SCC1PB+$8C ; SCC1 TBUF1.bcnt1 EQU SCC1PB+$90 ; SCC1 TX_len1 EQU SCC1PB+$92 ; SCC1 Tx frame length counter IADDR11 EQU SCC1PB+$94 ; SCC1 Individual Addr. Filter 1 IADDR21 EQU SCC1PB+$96 ; SCC1 Individual Addr. Filter 2 IADDR31 EQU SCC1PB+$98 ; SCC1 Individual Addr. Filter 3 IADDR41 EQU SCC1PB+$9A ; SCC1 Individual Addr. Filter 4 BOFF_CNT1 EQU SCC1PB+$9C ; back off counter TADDR1_H1 EQU SCC1PB+$9E ; temp address (MSB) TADDR1_M1 EQU SCC1PB+$A0 ; temp address TADDR1_L1 EQU SCC1PB+$A2 ; temp address (LSB) * Program Specific Equates MBUFS EQU $05F0 ; Max Buffer Size = 1520 bytes SCC1VEC EQU $1e ; Vector for SCC1 (5 bits) * Physical Address is 00-19-22-33-48-55 * This value is programmed into the PADDR entries in the parameter RAM * table in a byte-reversed manner. * The SADDR is the "source address" for our demo frames. * DADDR is the "destination address" for our demo frames. If the code is * in loopback, send frames with the same source and destination address. * Note that the byte order is different in the frame configuration than * in the PADDR entry in the parameter RAM. SADDRL EQU $0019 SADDRM EQU $2233 SADDRH EQU $4855 DADDRL EQU $0019 DADDRM EQU $2233 DADDRH EQU $4855 ********* * Start of Program ********* ORG INIT *** Get Pointer to Base of DPRAM and place it in a5 move.l #7,d0 ; "0111" is the function code for CPU Space movec d0,SFC ; Store "0111" into both the Src Fcn Code Reg movec d0,DFC ; and the Dest. Fcn Code Reg moves.l MBAR,a0 ; Move MBAR into a0 move.l a0,d0 andi.l #$ffffe000,d0 ; Extract the base address from MBAR move.l d0,a5 ; Move it to a5 for register indexing *** Set up SDMA Control Register for SCCs move.w #$0740,SDCR(a5) ; SDMA interrupt service mask = 7, * ; bus arbit. priority = 4 *** Set up Port A Pins * to get PA0, PA1, PA8, and PA9 to be RXD1, TXD1, CLK1, and CLK2 * we set PAPAR, PADIR, and PAODR as in Table 7-16 on page 7-351. or.w #$0303,PAPAR(a5) ; bits 1,2,8,& 9 must be 1 and.w #$FFFD,PAODR(a5) ; bit 2 must be zero (no open dr) and.w #$FCFC,PADIR(a5) ; bits 1,2,8, &9 must be 0 *** Set up Port C pins * to get PC4&PC5 to be CTS1&CD1 and PC0 to be RTS1, * we set PCPAR, PCDIR, and PCODR as in Table 7-18 on page 7-358. *** Fix 11/8/94 *** * must set PC2 high (EEST SC2) to get EEST out of staandby mode * must set PC7 high (EEST APEN) to allow auto port selection * also enable other EEST specific lines * PC3=TPEN = output from EEST. Ignored * PC8=TPACE = Set to 1 * PC9=TPSQEL = Set to 1 (active low in EEST) * PC10=TPFLDL = Set to 1 (active low in EEST) * PC11=LOOP = Set to 0 *** end fix * However, we don't want to enable PC0(TENA) yet. and.w #$F043,PCPAR(a5) ; bits 2,3,4,5,7,8-11 must = 0 or.w #$0000,PCPAR(a5) ; and bit 0 must =1 * ; but we will set that later and.w #$FFC6,PCDIR(a5) ; bits 3,4,5 and 0 = 0 or.w #$0F84,PCDIR(a5) ; bits 2,7,8-11 must = 1 or.w #$0030,PCSO(a5) ; bits 4&5 must = 1 * ; bit 0 is a don't care and.w #$FF73,PCSO(a5) ; bit 2,3,7 should = 0 and.w #$FFFB,PCDAT(a5) ; bit 2 must be zero or.w #$0780,PCDAT(a5) ; bits 7,8-9 must be 1 * this example is running in normal mode, (which requires external * clocking from the SIA.) In order to use it in loopback, you have to * provide clocks. The demo code can be modified to do this by * removing the '*'s from the third and fourth lines and commenting * out the second line. and.l #$FFFFFF00,SICR(a5) ; clear SCC1 entries in SICR or.l #$00000025,SICR(a5) ; route CLK1+2 to SCC1 and select NMSI pins * ; RCLK1=CLK1. TCLK1=CLK2. * ; Note that external clocks MUST be provided * ; for any transmission/reception to happen * move.l #$00010004,BRGC2(a5) ; if you want to use loopback mode, you have * or.l #$00000009,SICR(a5) ; generate an int. clock. BRGC2 is generating * ; a clock and this clk is routed to RCLK and * ; TCLK of SCC1. The BRG clock will generate a * ; frequency of 25Mhz/(2+1)=8.33Mhz *** Set up General SCC Parameters move.w #$0000,RBASE1(a5) ; Receive BDs start at 0(a5) move.w #$0020,TBASE1(a5) ; Transmit BDs start at 32(a5) move.b #$18,RFCR1(a5) ; mot=1(msbyte first), rx function code = 1000 move.b #$18,TFCR1(a5) ; mot=1(msbyte first), tx function code = 1000 move.w #MBUFS,MRBLR1(a5) ; max. bytes per Buffer=MBUFS *** Execute the INIT RX & TX Parameters for SCC1 move.w #$0001,CR(a5) ; initialize transmit and receive parameter * ; in the parameter ram of scc1 *** Set up Ethernet Specific Parameters move.l #$DEBB20E3,C_MASK1(a5) ; required setting for 32 Bit CCITT CRC move.l #$FFFFFFFF,C_PRES1(a5) ; required setting for 32 Bit CCITT CRC move.l #$0,CRCEC1(a5) ; clear CRC Error Counter move.l #$0,ALEC1(a5) ; clear Alignment Error Counter move.l #$0,DISFC1(a5) ; clear Discarded Frame Error Counter move.w #$8888,PADS1(a5) ; pad character pattern (standard value) move.w #$000F,RET_Lim1(a5) ; Retry Limit (standard value) move.w #$05EE,MFLR1(a5) ; Max Frame Length (standard value) move.w #$0040,MINFLR1(a5) ; Min Frame Length (64 is standard) move.w #$05EE,MAXD11(a5) ; user tunable parameters move.w #$05EE,MAXD21(a5) ; see page 7-255 move.w #$05EE,DMA_cnt1(a5) ; set to same as MFLR1 move.w #$0,GADDR11(a5) move.w #$0,GADDR21(a5) ; reset to zero before entering move.w #$0,GADDR31(a5) ; values into table move.w #$0,GADDR41(a5) move.w #$5548,PADDR1_H1(a5) ; This station address is move.w #$3322,PADDR1_M1(a5) ; 00-19-22-33-48-55 where 00 move.w #$1900,PADDR1_L1(a5) ; is the low order byte move.w #$0000,P_PER1(a5) ; User tunable parameter move.w #$0,IADDR11(a5) move.w #$0,IADDR21(a5) ; reset to zero before move.w #$0,IADDR31(a5) ; entering values into table move.w #$0,IADDR41(a5) move.w #$0,TADDR1_H1(a5) move.w #$0,TADDR1_M1(a5) ; used for entry into table move.w #$0,TADDR1_L1(a5) *** Set up the Receive BDs * (set the ready bit after the Buffer pointer is set up) move.l a5,a0 add.w RBASE1(a5),a0 ; make pointer to Receive BDs * BD1 clr.w 2(a0) ; initialize length move.l #RXBUF+0*MBUFS,4(a0) ; pointer to buffer number 0 move.w #$9000,(a0) ; empty, nowrap, int * BD2 clr.w 10(a0) ; initialize length move.l #RXBUF+1*MBUFS,12(a0) ; pointer to buffer number 1 move.w #$9000,8(a0) ; empty, nowrap, int * BD3 clr.w 18(a0) ; initialize length move.l #RXBUF+2*MBUFS,20(a0) ; pointer to buffer number 2 move.w #$9000,16(a0) ; empty, nowrap, int * BD4 clr.w 26(a0) ; initialize length move.l #RXBUF+3*MBUFS,28(a0) ; pointer to buffer number 3 move.w #$b000,24(a0) ; empty, wrap, int *** Set up Process Receive Data Pointer (part of interrupt service routine) move.w RBASE2(a5),PRDPTR ; PRDPTR points to BD#1 *** Set up Transmit BDs * (set the ready bit after the Buffer pointer & length is set up) movea.l a5,a0 ; get pointer to base of DPRAM adda.w TBASE1(a5),a0 ; make pointer to Transmit BDs * BD1 move.w #(TBUF1-TBUF0),2(a0) ; length 13 move.l #TBUF0,4(a0) ; pointer to buffer #0 move.w #$CC00,(a0) ; ready, pad, nowrap, noint, Xmit CRC, Last * BD2 move.w #(TBUF2-TBUF1),10(a0) ; length 13 move.l #TBUF1,12(a0) ; pointer to buffer #1 move.w #$CC00,8(a0) ; ready, pad, nowrap, noint, Xmit CRC, Last * BD3 move.w #(TBUF3-TBUF2),18(a0) ; length 13 move.l #TBUF2,20(a0) ; pointer to buffer #2 move.w #$CC00,16(a0) ; ready, pad, nowrap, noint, Xmit CRC, Last * BD4 move.w #(TBUF4-TBUF3),26(a0) ; length 13 move.l #TBUF3,28(a0) ; pointer to buffer #3 move.w #$EC00,24(a0) ; ready, pad, nowrap, noint, Xmit CRC, Last *** Set up Vector Table, Configure SCC1 to be SCCa. * * Set up CICR. (In most situations, the VBA2-0 bits and the IRL2-0 bits * would be set by the kernal and the SCC Priority bits would be set * by the SCC control program ("user code")). The QUADS boot rom * does not set up this register so this code will do both in separate * steps. * kernel step move.l #$00008040,CICR(a5) ; Int Level=4, Vec Base=2 * ; *note* VEC BASE Must Be >=2 * user steps move.l CICR(a5),d0 ; get CICR andi.l #$0000e0e0,d0 ; mask out all but IRL & VBA clr.l d1 move.b d0,d1 ; store copy of VBA ori.l #$00931f00,d0 ; Priority=4,1,2,3; Std HP * ; Grouped SCCs move.l d0,CICR(a5) * now calculate the Vector Table Location for SCCa Exception Vector ori.b #SCC1VEC,d1 ; concatenate VBA with Vec Num asl.l #2,d1 ; create offset into vector table movec.l VBR,a4 ; get Vector Base Register move.l #SCC1INT,0(a4,d1) ; put address of service routine * ; into vector table *** Final Set up move.w #$ffff,SCCE1(a5) ; clear scc1 event register move.w #$0009,SCCM1(a5) ; enable rxf and rxb interrupts ori.l #$40000000,CIMR(a5) ; Allow SCC1 interrupts andi.w #$f8ff,SR ; Set CPU IMASK to 0 move.l #$00000000,GSMR_H1(a5) * move.l #$1088004C,GSMR_L1(a5) ; SCC1 conf. reg. set to automatic * ; control of CLSN and RENA, more setup * ; time for the EEST, loopback and ethernet mode. * ; ENR and ENT are not enabled yet. move.l #$1088000C,GSMR_L1(a5) ; SCC1 conf. reg. set to automatic * ; control of CLSN and RENA, more setup * ; time for the EEST and ethernet mode. * ; ENR and ENT are not enabled yet. * move.w #$2A4A,PSMR1(a5) ; ethernet mode reg. is set to receive * ; short frames, 32 bit CRC, reject all frames, * ; loop operation and begin searching for the * ; start frame delimiter 22 bits after RENA move.w #$2A0A,PSMR1(a5) ; ethernet mode reg. is set to receive * ; short frames, 32 bit CRC, reject all frames, * ; and begin searching for the * ; start frame delimiter 22 bits after RENA MOVE.W #$D555,DSR1 move.w #$D555,DSR1(a5) or.w #$0001,PCPAR(a5) ; enable TENA ori.l #$00000030,GSMR_L2(a5) ; enable transmitter and receiver self jmp self **** SCC1 Interrupt Routine * The framework for this routine can be found on page D-12 of the 68302 UM * It has been changed to accomodate CM mode. The condition for stopping * is no longer the E bit set (because in CM mode, the E bit is ALWAYS set) * The BD processing now stops when PRDPTR=RBPRT1. ***Note that RBPRT1 is * now an offset into DPRAM rather than the BD number (1..8) SCC1INT movem.l d0-d2/a0-a2,-(a7) ; save context registers move.w SCCE1(a5),-(a7) ; temporarily store SCC event * ; register on stack move.w #$ffff,SCCE1(a5); Clear all SCC events move.w (a7),d2 ; get a copy of the register andi.w #9,d2 ; is RXF or RXB set? beq INT1 bsr REC_BD ; if so, process the BDs INT1 move.l #$40000000,CISR(a5) ; clear SCC1 bit in ISR move.w (a7)+,d2 ; remove SCCE1 from stack movem.l (a7)+,d0-d2/a0-a2 ; Restore Context rte REC_BD move.w PRDPTR,d0 move.l a5,a0 ; REPEAT--UNTIL style loop add.w d0,a0 ; a0 is absolute pointer to unprocessed BD move.w (a0),d0 ; get copy of BD status word andi.w #$00ff,d0 ; save error indicators bne ERR_HAND ; branch to error handler if errors * ** Process the received data here * CONT clr.w 2(a0) ; Clear the length word andi.w #$f000,(a0) ; clear status bits bset.b #7,(a0) ; Set the Empty Bit btst.b #5,(a0) ; Is the wrap bit set? bne WRAP_R ; if so, point PRD to RBASE addq.w #$8,PRDPTR ; else increment PRDPTR to next BD bra CHKMOR ; and check the next BD WRAP_R move.w RBASE1(a5),PRDPTR CHKMOR move.w PRDPTR,d0 ; put PRDPTR into d0 cmp.w RBPRT1(a5),d0 ; if PRDPTR=RBPRT1 bne REC_BD rts ; done servicing RXB/RXF *** Error Handler Ignores Receive Errors ERR_HAND bra CONT **** demo data ORG INIT+$2000 RXBUF: ds.b MBUFS*4 ; reserve space for 4 buffers *put data in send buffers TBUF0: dc.w DADDRL,DADDRM,DADDRH ; dest address dc.w SADDRL,SADDRM,SADDRH ; source address dc.b 12 ; length dc.b 'Frame 1 data' TBUF1: dc.w DADDRL,DADDRM,DADDRH ; dest address dc.w SADDRL,SADDRM,SADDRH ; source address dc.b 12 ; length dc.b 'Frame 2 data' TBUF2: dc.w $0000,0000,0000 ; dest address dc.w SADDRL,SADDRM,SADDRH ; source address dc.b 16 ; length dc.b 'Unreceived Frame' TBUF3: dc.w $ffff,$ffff,$ffff ; broadcast address dc.w SADDRL,SADDRM,SADDRH ; source address dc.b 12 ; length dc.b 'Frame 4 data' TBUF4: * ; Dummy label PRDPTR: ds.w 1 ; pointer to next Receive BD to * ; process END