*****************************************************************
*    PIT Example Code                                           *
*    Creates a PIT interrupt and toggles PB0 during servicing   *
*    to create a square wave output                             *
*                                                               *
*    The PIT interrupt time is dependent upon the PIT register  *
*    settings and SPCLK (which is determined by the system      *
*    clock speed and the MODCK1-0 bits).                        *
*                                                               *
*    SPCLK is described on p. 6-17 of the 68360 UM and the      *
*    UM errata sheet                                            *
*    The PIT period is described on p. 6-11 of the UM           *
*                                                               *
*    When this code is run on a 25 MHz QUADS board (which sets  *
*    MODCK1-0=01), PB0 will output a square wave with a period  *
*    of 820 us.                                                 *
* JS 10/21/93                                                   *
* updated 7/14/94                                               *
*****************************************************************
******* Board Specific Equate
INIT    EQU     $403000         ; QUADS board DRAM user space
******* Equates
MBAR    EQU     $03FF00         ; Module Base Address Register
***********************************************************************
* The following equates assume that they will be used in register
* indirect addressing.  The address register  should hold the base
* address of the QUICC internal memory.  All system equates are
* offsets into this memory
REGB    EQU     $1000           ; Base offset of Internal Registers
PICR    EQU     REGB+$0026      ; Periodic Interrupt Control
PITR    EQU     REGB+$002A      ; Periodic Interrupt Timing
PBDIR   EQU     REGB+$06B8      ; Port B Data Direction Assignment
PBPAR   EQU     REGB+$06BC      ; Port B Pin Function Assignment
PBODR   EQU     REGB+$06C2      ; Port B Open Drain Assignment
PBDAT   EQU     REGB+$06C4      ; Port B Data Content
*
*** Program Specific Equate
PITVEC  EQU     64              ; Vector 64 in points to PIT Routine

        ORG     INIT
*** Get Pointer to Base of DPRAM
        move.l  #7,d0           ; "0111" is the function code for CPU Space
        movec   d0,SFC          ; Store "0111" into both the Src Fcn Code Reg
        movec   d0,DFC          ; and the Dest. Fcn Code Reg
        moves.l MBAR,a0         ; Move MBAR into a0
        move.l  a0,d0
        andi.l  #$ffffe000,d0   ; Extract the base address from MBAR
        move.l  d0,a5           ; Move it to a5 for register indexing

*** Set up PB0 to be parallel output
        and.w   #$FFFE,PBODR(a5)        ; Set PB0 to be driven output
        or.l    #$00000001,PBDIR(a5)    ; Set PB0 to be output
        and.l   #$FFFFFFFE,PBPAR(a5)    ; Set PB0 to be I/O
        or.l    #$00000001,PBDAT(a5)    ; Initialize PB0 to be a 1


*** Set up Vector Table
*
        movec.l VBR,a4                  ; get Vector Base Register
        move.l  #PITVEC,d0
        asl.l   #2,d0                   ; create offset into vector table
        move.l  #PITINT,0(a4,d0)        ; put address of service routine
*                                       ; into vector table

*** Set Up PIT Timer Register

        move.w  #$0214,PITR(a5)         ; PTP=0,SWP=1, Count of 20
        move.w  #PITVEC,d0              ; get PITVEC for PIV bits
        or.w    #$0500,d0               ; set PIRQL to 5
        andi.w  #$f8ff,SR
        ori.w   #$0300,SR               ; Set System IMASK Lower than 5
        move.w  d0,PICR(A5)             ; start PIT running

self    bra     self                    ; loop forever


*** Interrupt Routine

PITINT  bchg.b  #0,PBDAT+3(a5)          ; toggle PB0
        RTE                             ; return from exception
END