/*********************************************************************** 
* NOTICE
* All files contained on this disk are subject to the licensing conditions
* issued by MOTOROLA Inc.
*
* All files are copyright 1993 by MOTOROLA Inc. 
************************************************************************/

/*
 * bss.h
 * definition of the driver module's work area
 * (per instantiation and global)
 */

#define	CR_WAIT		1000

/*
 * There is actually room for 11 conf pointers
 * in the GWA (this is the only limitting factor
 * on the number of QUICC's supported).
 * We set it at 8 as a reasonable limit, with
 * room for growth/error (!).
 */
#define	MAX_QUICCS	8	/* maximum number of QUICC's supported */


/*
 * driver's global work area
 * (used by all children)
 */
typedef struct gwa {
	unsigned short		num_timers;
	struct timer {
		struct t_table *timer_table;	/* ptr to timer table */
		unsigned short	resolution;	/* # of ticks/scan */
		unsigned short	tick_counter;	/* ticks/scan counter */
	} *timer;			/* points to timer table */

	unsigned short	trace_mask;	/* selective event tracing */
	unsigned long	intr_trace;	/* QUICC interrupt tracing */
	unsigned char	soh;		/* Bisync SOH character */
	unsigned char	stx;		/* Bisync STX character */
	unsigned char	etx;		/* Bisync ETX character */
	unsigned char	eot;		/* Bisync ETX character */
	long		timer_tick;	/* dummy timer message */
	long		timer_poll;	/* dummy polling message */
	struct driver_config	*conf[MAX_QUICCS];/* max # of 360's */
} GWA;


/*
 * receive error mask bits
 * lower (6) bits are defined as in RX BD status
 */
#define	R_BUSY		0x8000


/*
 * per child flag bits
 */
#define	TX_STOPPED	0x0001		/* need restart-tx cmd */
#define	RX_DISABLE	0x0002		/* rx process disabled */
#define	RX_ACTIVATE	0x0004		/* activate rx (once) */
#define	CONF_DISABLE	0x0008		/* conf process disabled */
#define	CONF_ACTIVATE	0x0010		/* activate conf (once) */
#define	LOCAL_BUSY	0x0020		/* local busy set */
#define	POOL_EMPTY	0x0040		/* pool size less than min */
#define	UART_CHARMODE	0x0080		/* uart: use character mode */
#define	DLE_RECEIVED	0x0080		/* bisync: dle was received */
#define	INFRAME		0x0100		/* bisync: not start of block */
#define	DMA_IDLE	0x0080		/* dma multi buff: idma idle */
#define	DMA_STARTED	0x0200		/* dma: single buffer mode */
#define	DMA_TOPERIPH	0x0100		/* dma operations to peripheral */
#define	LOOP_MODE	0x8000		/* loopback */

/*
 * More flags per child
 */
#define	SCC_TTX		0x0001		/* SCC transmit transparent */
#define	SCC_TRX		0x0002		/* SCC receive transparent */
#define	SCC_TTXRX	0x0003		/* SCC receive transparent */
#define	SCC_TOD		0x0004		/* SCC transmit on demand */
#define	SMC_GCI		0x0010		/* SMC gci mode */


/*
 * per instantiation structure
 */
typedef struct work_area {
	unsigned short	channel;	/* channel: 1-4 SCC's, 1-2 DMA & SMC*/
	unsigned short	rxerr_mask;	/* receive error mask */
	struct t_frame	*conf_q;	/* next frame for conf */
	struct t_frame	*tx_q;		/* next frame for tx */
	struct t_frame	*req_q;		/* last requested frame */
	struct r_frame	*rx_q;		/* next frame for rx */
	struct r_frame	*pool_q;	/* first frame in pool */
	struct r_frame	*rtp_q;		/* end of pool (return to pool here) */
	struct quicc	*quicc;		/* base address of QUICC */
	struct scc_pram	*pram;		/* port's parameter RAM */
	struct ethernet_pram	*enet_pram;	/* port's parameter RAM */
	struct scc_regs	*regs;		/* port's SCC registers */
	struct quicc_bd	*quicc_tbd;	/* next tx BD in table to use */
	struct quicc_bd	*quicc_cbd;	/* next conf BD in table to use */
	struct quicc_bd	*quicc_rbd;	/* next BD in table for rx */
	struct quicc_bd	*quicc_pbd;	/* next BD in table for pool buffer */
	char		tsize;		/* number of Bd's in tx table */
	char		tfree;		/* free BD slots */
	char		rsize;		/* rx table size */
	char		rfree;		/* free BD's in rx table */
	unsigned long	tcount;		/* number of frames tx-ed */
	unsigned long	rcount;		/* number of frames rx-ed */
	unsigned long	terr_cnt;	/* number of transmit errors */
	unsigned long	rerr_cnt;	/* number of receive errors */

	unsigned char	pool_cnt;	/* num of bufs in pool */
	unsigned char	minpool;	/* min buffers in pool */
	unsigned short	fr_lng;		/* max frame length */
	unsigned short	rlen;		/* rx buffer length */
	unsigned short	intr_trace;	/* event tracing */

	unsigned short	BDfirst;	/* first BD's in frames flags */
	unsigned short	BDlast;		/* last BD's in frames flags */
	unsigned short	BDrx;		/* status bits for rx BD's*/

	unsigned short	intr_rxfr;	/* rx frame interrupt mask */
	unsigned short	intr_txbd;	/* tx BD interrupt mask */
	unsigned short	intr_terr;	/* tx error interrupt mask */
	unsigned short	intr_busy;	/* busy interrupt mask */

	unsigned long	rxind_event;	/* dummy RXIND msg */
	unsigned long	txconf_event;	/* dummy TX_CONF msg */
	unsigned long	txe_event;	/* dummy TX_ERR msg */
	unsigned long	busy_event;	/* dummy BUSY msg */

	unsigned short	more_flags;	/* More flags for the child */
	unsigned char	max_ind_addr;	/* Max individual addresses */
	unsigned char	max_grp_addr;	/* Max group addresses */
	struct enet_addr	*ind_addrs;/* individual addr table */
	struct enet_addr	*grp_addrs;/* group addr table */
	unsigned short	t_error;	/* BD transmit error */
} WORK_AREA;