/*********************************************************************** * NOTICE * All files contained on this disk are subject to the licensing conditions * issued by MOTOROLA Inc. * * All files are copyright 1993 by MOTOROLA Inc. ************************************************************************/ /* * config.h * this file contains definitions * for the use of the QUICC driver * configuration. */ /* * protocol specific parameter ram * initialization. */ struct hpram { unsigned long c_mask; /* CRC constant */ unsigned long c_pres; /* CRC preset */ unsigned short disfc; /* discard frame counter */ unsigned short crcec; /* CRC error counter */ unsigned short abtsc; /* Abort sequence counter */ unsigned short nmarc; /*nonmatching address rx count*/ unsigned short retrc; /*frame retransmission counter*/ unsigned short mflr; /* max frame length register */ unsigned short rfthr; /* received frames threshold */ unsigned short hmask; /*user defined frame addr mask*/ unsigned short haddr1; /*user defined frame address 1*/ unsigned short haddr2; /*user defined frame address 1*/ unsigned short haddr3; /*user defined frame address 1*/ unsigned short haddr4; /*user defined frame address 1*/ }; struct upram { unsigned short max_idl; /* maximum number of idles */ unsigned short brkcr; /* break count register */ unsigned short parec; /* Rx parity error counter */ unsigned short frmer; /* Rx framing error counter */ unsigned short nosec; /* Rx noise counter */ unsigned short brkec; /* Rx break character counter */ unsigned short uaddr1; /* address check char #1 */ unsigned short uaddr2; /* address check char #2 */ unsigned short toseq; /* Tx out of sequence char */ unsigned short cc[8]; unsigned short rccm; /* Rx control char mask */ }; struct bpram { unsigned short prcrc; /* preset rx CRC value */ unsigned short ptcrc; /* preset tx CRC value */ unsigned short bsync; /* SYNC character */ unsigned short bdle; /* DLE character */ unsigned short cc[8]; /* control characters */ unsigned short rccm; /* Rx Control Chararacter Mask */ }; struct dpram { unsigned short pcrc; /* preset CRC value */ unsigned short soh; /* SOH character */ unsigned short enq; /* ENQ character */ unsigned short dle; /* DLE character */ unsigned short r_max; /* maximum frame length */ unsigned short r_mask; /* address mask */ unsigned short r_addr1; /* address 1 */ unsigned short r_addr2; /* address 2 */ unsigned short r_addr3; /* address 3 */ unsigned short r_addr4; /* address 4 */ }; struct epram { unsigned long c_mask; /* constant mask for CRC */ unsigned long c_pres; /* preset CRC */ unsigned long crcec; /* CRC error counter */ unsigned long alec; /* alighnment error counter */ unsigned long disfc; /* discard frame counter */ unsigned short pads; /* short frame PAD characters */ unsigned short ret_lim; /* retry limit threshold */ unsigned short mflr; /* maximum frame length reg */ unsigned short minflr; /* minimum frame length reg */ unsigned short maxd1; /* maximum DMA1 length reg */ unsigned short maxd2; /* maximum DMA2 length reg */ unsigned short gaddr1; /* group address filter 1 */ unsigned short gaddr2; /* group address filter 2 */ unsigned short gaddr3; /* group address filter 3 */ unsigned short gaddr4; /* group address filter 4 */ unsigned short paddr_h; /* physical address (MSB) */ unsigned short paddr_m; /* physical address */ unsigned short paddr_l; /* physical address (LSB) */ unsigned short p_per; /* persistence */ unsigned short iaddr1; /* individual address filter 1*/ unsigned short iaddr2; /* individual address filter 2*/ unsigned short iaddr3; /* individual address filter 3*/ unsigned short iaddr4; /* individual address filter 4*/ unsigned short taddr_h; /* temp address (MSB) */ unsigned short taddr_m; /* temp address */ unsigned short taddr_l; /* temp address (LSB) */ }; struct smc_upram { unsigned short max_idl; /* maximum number of idles */ unsigned short brkln; /* Last Received Break Len */ unsigned short brkec; /* Rx break character counter */ unsigned short brkcr; /* Break Count Register (Tx) */ }; struct driver_config { int index; /* for multi-quicc applications */ unsigned rom; /* base address in ROM */ int max; /* max number of children */ unsigned short num_timers; /* # of timers to support */ struct quicc *internal_ram; /* address of internal RAM */ unsigned short trace_mask; /* event tracing */ unsigned short intr_trace; /* QUICC interrupt tracing */ /* configuration control */ unsigned long bar; /* base address register */ /* sim */ unsigned long sim_mcr; /* module configuration reg */ unsigned short sim_simtr; /* module test register */ unsigned char sim_avr; /* auto vector reg */ unsigned char sim_clkocr; /* CLCO control register */ unsigned short sim_pllcr; /* PLL control register */ unsigned short sim_cdvcr; /* Clock devider control register */ unsigned short sim_pepar; /* Port E pin assignment register */ unsigned char sim_sypcr; /* system protection control */ unsigned char sim_swiv; /* software interrupt vector */ unsigned short sim_picr; /* periodic intrpt cntrl reg */ unsigned short sim_pitr; /* periodic intrpt timing reg */ unsigned char sim_swsr; /* software service */ unsigned long sim_bkar; /* breakpoint address regiter */ unsigned long sim_bkcr; /* breakpoint control regiter */ /* memc */ unsigned long memc_gmr; /* Global memory register */ unsigned long memc_br0; /* base register 0 */ unsigned long memc_or0; /* option register 0 */ unsigned long memc_br1; /* base register 1 */ unsigned long memc_or1; /* option register 1 */ unsigned long memc_br2; /* base register 2 */ unsigned long memc_or2; /* option register 2 */ unsigned long memc_br3; /* base register 3 */ unsigned long memc_or3; /* option register 3 */ unsigned long memc_br4; /* base register 4 */ unsigned long memc_or4; /* option register 4 */ unsigned long memc_br5; /* base register 5 */ unsigned long memc_or5; /* option register 5 */ unsigned long memc_br6; /* base register 6 */ unsigned long memc_or6; /* option register 6 */ unsigned long memc_br7; /* base register 7 */ unsigned long memc_or7; /* option register 7 */ /* idma */ unsigned short idma_iccr; /* channel configuration reg */ struct idma { struct quicc *quicc; /* sometimes redundant */ unsigned char child_id; /* id */ unsigned char upper; /* upper module */ char isize; /* number of buffers */ /* IDMA Registers */ unsigned short idma_cmr;/* idma mode register */ unsigned long idma_sapr;/* idma source address reg */ unsigned long idma_dapr;/* idma destination address */ unsigned long idma_bcr;/* idma byte count register */ unsigned char idma_fcr;/* idma function code reg */ unsigned char idma_cmar;/* channel mask register */ unsigned char idma_csr;/* channel mask register */ /* IDMA parameters ram */ unsigned short ibase; /* IDMA BD Base Address */ } idma[2]; /* sdma */ unsigned short sdma_sdcr; /* configuration reg */ unsigned long sdma_sdar; /* address reg */ /* interrupt controller */ unsigned long intr_cicr; /* CP interrupt confing reg*/ unsigned long intr_cimr; /* CP interrupt mask reg*/ /* parallel I/O */ unsigned short pio_padir; /* port A data direction reg */ unsigned short pio_papar; /* port A pin assignment reg */ unsigned short pio_paodr; /* port A open drain reg */ unsigned short pio_padat; /* port A data register */ unsigned short pio_pcdir; /* port C data direction reg */ unsigned short pio_pcpar; /* port C pin assignment reg */ unsigned short pio_pcso; /* port C special options */ unsigned short pio_pcdat; /* port C data register */ unsigned long pio_pcint; /* port C mode reg */ /* timer */ unsigned short timer_tgcr; /* timer global config reg */ unsigned short timer_tmr1; /* timer 1 mode reg */ unsigned short timer_tmr2; /* timer 2 mode reg */ unsigned short timer_trr1; /* timer 1 referance reg */ unsigned short timer_trr2; /* timer 2 referance reg */ unsigned short timer_tmr3; /* timer 3 mode reg */ unsigned short timer_tmr4; /* timer 4 mode reg */ unsigned short timer_trr3; /* timer 3 referance reg */ unsigned short timer_trr4; /* timer 4 referance reg */ /* cp */ unsigned short cp_cr; /* command register */ unsigned short cp_rccr; /* main configuration reg */ unsigned long cp_rmdr; /* devlp support control reg */ unsigned short cp_cpcr1; /* CP Control Register 1 */ unsigned short cp_cpcr2; /* CP Control Register 2 */ unsigned short cp_cpcr3; /* CP Control Register 3 */ unsigned short cp_cpcr4; /* CP Control Register 4 */ unsigned short cp_rtmr; /* main timers mask reg */ /* brg */ unsigned long brgc1; /* BRG1 configuration reg */ unsigned long brgc2; /* BRG2 configuration reg */ unsigned long brgc3; /* BRG3 configuration reg */ unsigned long brgc4; /* BRG4 configuration reg */ struct scc { struct quicc *quicc; /* sometimes redundant */ short child_id; char loop_mode; /* id for loopback (-1 if not) */ char upper; char tsize; /* number of tx buffers */ char rsize; /* number of rx buffers */ short minpool; /* min buffers in pool */ short psize; /* # of buffers in pool */ short rxerr_mask; /* receive error mask */ short intr_trace; /* event tracing */ unsigned char max_ind_addr; /* Max individual addresses */ unsigned char max_grp_addr; /* Max group addresses */ /* SCC common protocol parameters */ unsigned long scc_gsmra; /* SCC general mode reg */ unsigned long scc_gsmrb; /* SCC general mode reg */ unsigned short scc_psmr; /* SCC mode register */ unsigned short scc_dsr; /* SCC data sync reg */ unsigned short scc_sccm; /* SCC mask reg */ unsigned short rbase; /* rx BD base address */ unsigned short tbase; /* tx BD base address */ unsigned char rfcr; /* rx function code */ unsigned char tfcr; /* tx function code */ unsigned short mrblr; /*max rx buffer length*/ unsigned short rbptr; /* RX BD pointer */ unsigned short tbptr; /* TX BD pointer */ unsigned long crc_p; /* CRC preset for transparent */ unsigned long crc_c; /* CRC constnt for transparent*/ /* * protocol specific parameter ram */ union { struct hpram h; struct upram u; struct bpram b; struct dpram d; struct epram e; } pram; } scc[4]; /* smc */ struct smc { struct quicc *quicc; /* sometimes redundant */ short child_id; char loop_mode; /* id for loopback (-1 if not) */ char upper; char tsize; /* number of tx buffers */ char rsize; /* number of rx buffers */ short minpool; /* min buffers in pool */ short psize; /* # of buffers in pool */ short rxerr_mask; /* receive error mask */ short intr_trace; /* event tracing */ /* SMC common protocol parameters */ unsigned short smc_smcmr; /* SMC mode reg */ unsigned char smc_smce; /* SMC event reg */ unsigned char smc_smcm; /* SMC mask reg */ /* SMC Parameter Ram */ unsigned short rbase; /* rx BD base address */ unsigned short tbase; /* tx BD base address */ unsigned char rfcr; /* rx function code */ unsigned char tfcr; /* tx function code */ unsigned short mrblr; /*max rx buffer length*/ unsigned short rbptr; /* RX BD pointer */ unsigned short tbptr; /* TX BD pointer */ /* * protocol specific parameter ram */ union { struct smc_upram u; } pram; } smc[2]; /* spi */ struct spi { struct quicc *quicc; /* sometimes redundant */ short child_id; char upper; short rxerr_mask; /* receive error mask */ short intr_trace; /* event tracing */ /* parameter ram */ unsigned short rbase; /* rx BD base address */ unsigned short tbase; /* tx BD base address */ unsigned char rfcr; /* rx function code */ unsigned char tfcr; /* tx function code */ unsigned short mrblr; /*max rx buffer length*/ /* SPI registers */ unsigned short spi_spmode; /* SPI mode reg */ unsigned short spi_spim; /* SPI mask reg */ }spi; /* PIP */ unsigned short pip_pipc; /* pip configuration reg */ unsigned short pip_ptpr; /* pip timing parameters reg */ unsigned long pip_pbdir; /* port b data direction reg */ unsigned long pip_pbpar; /* port b pin assignment reg */ unsigned long pip_pbodr; /* port b open drain reg */ unsigned long pip_pbdat; /* port b data reg */ /* Serial Interface */ unsigned long si_simode; /* SI mode register */ unsigned char si_sigmr; /* SI global mode register */ unsigned long si_sicr; /* SI clock routing */ };