/*********************************************************************** 
* NOTICE
* All files contained on this disk are subject to the licensing conditions
* issued by MOTOROLA Inc.
*
* All files are copyright 1993 by MOTOROLA Inc. 
************************************************************************/

/*
 * Definitions for IDMA
 */

/*
 * Mascros for accesing to IDMA registers
 * using the structure QUICC
 */

#define IDMA_CMR(i)	(i ? quicc->idma2_cmr :	quicc->idma1_cmr)
#define IDMA_SAPR(i)	(i ? quicc->idma2_sapr : quicc->idma1_sapr)
#define IDMA_DAPR(i)	(i ? quicc->idma2_dapr : quicc->idma1_dapr)
#define IDMA_BCR(i)	(i ? quicc->idma2_bcr : quicc->idma1_bcr)
#define IDMA_FCR(i)	(i ? quicc->idma2_fcr : quicc->idma1_fcr)
#define IDMA_CMAR(i)	(i ? quicc->idma2_cmar : quicc->idma1_cmar)
#define IDMA_CSR(i)	(i ? quicc->idma2_csr : quicc->idma1_csr)

#define IDMA_CMR_WRT(i,exp)	(i ? (quicc->idma2_cmr = exp)\
					: (quicc->idma1_cmr = exp))
#define IDMA_SAPR_WRT(i,exp)	(i ? (quicc->idma2_sapr = exp)\
					: (quicc->idma1_sapr = exp))
#define IDMA_DAPR_WRT(i,exp)	(i ? (quicc->idma2_dapr = exp)\
					: (quicc->idma1_dapr = exp))
#define IDMA_BCR_WRT(i,exp)	(i ? (quicc->idma2_bcr = exp)\
					: (quicc->idma1_bcr = exp))
#define IDMA_FCR_WRT(i,exp)	(i ? (quicc->idma2_fcr = exp)\
					: (quicc->idma1_fcr = exp))
#define IDMA_CMAR_WRT(i,exp)	(i ? (quicc->idma2_cmar = exp)\
					: (quicc->idma1_cmar = exp))
#define IDMA_CSR_WRT(i,exp)	(i ? (quicc->idma2_csr = exp)\
					: (quicc->idma1_csr = exp))

#define IDMA_CMR_ADR(i)	(i ? &quicc->idma2_cmr :&quicc->idma1_cmr)
#define IDMA_SAPR_ADR(i) (i ? &quicc->idma2_sapr : &quicc->idma1_sapr)
#define IDMA_DAPR_ADR(i) (i ? &quicc->idma2_dapr : &quicc->idma1_dapr)
#define IDMA_BCR_ADR(i)	(i ? &quicc->idma2_bcr : &quicc->idma1_bcr)
#define IDMA_FCR_ADR(i)	(i ? &quicc->idma2_fcr : &quicc->idma1_fcr)
#define IDMA_CMAR_ADR(i) (i ? &quicc->idma2_cmar : &quicc->idma1_cmar)
#define IDMA_CSR_ADR(i)	(i ? &quicc->idma2_csr : &quicc->idma1_csr)

/* IDMA Buffer Descriptors */
typedef struct idma_bd {
	unsigned short	status;
	unsigned short	filler;
	unsigned long	length;
	unsigned char	*sbuf;
	unsigned char	*dbuf;
} IDMA_BD;


/*****************************************************************
	dma mode register
*****************************************************************/

#define	ECO_BIT 0x8000
#define	RCI_BIT 0x1000
#define	RST_BIT 0x0002
#define	STR_BIT 0x0001

/*****************************************************************
	channel status register
*****************************************************************/

#define	DMA_AD_BIT	0x20
#define	DMA_BRKP_BIT	0x10
#define	DMA_OB_BIT	0x08
#define	DMA_BES_BIT	0x04
#define	DMA_BED_BIT	0x02
#define	DMA_DONE_BIT	0x01

/*
 * request generation
 */
#define	EXTERNAL_REQG   0x0800
#define INTREQ_LIM      0x0000
#define INTREQ_MAX      0x0400
#define EXTREQ_BURST    0x0800
#define EXTREQ_CYCL     0x0c00

/*****************************************************************
* IDMA BD's
*****************************************************************/
#define	I_V	0x8000		/* Valid bit */
#define	I_W	0x2000		/* wrap bit */
#define	I_I	0x1000		/* interrupt on completion */
#define	I_L	0x0800		/* last buffer to be transfered */
#define	I_CM	0x0200		/* continuous mode */
#define	I_SE	0x0004		/* source access bus error */
#define	I_DE	0x0002		/* destination access bus error */
#define	I_DA	0x0001		/* done asserted during transfer */

/* general command opcodes */
#define	INIT_IDMA		0x0500

/*****************************************************************
	ibase register
*****************************************************************/
#define IBD_ADDR(w)     ((struct idma_bd *) \
			(w->quicc->udata_bd_ucode +\
				w->pram->pothers.idma_smc.idma.ibase))