* * Header File for the QUICC ( MC68360 ) * Ethernet Example User's Manual Page 7-272 * PH 5/5/93 ************************************************************* * INIT EQU $0402000 ; QUADS Board DRAM User Space * ************************** DUAL PORT RAM MBAR EQU $03FF00 ; Module Base Address, (MBAR)=REGB MBARE EQU $03FF08 ; Module Base Address Enable SLAVE * DPRBASE EQU $00020000 ; Base address of dual-port RAM RXBD EQU DPRBASE+$0000 ; Receive Buffer Discriptor address TXBD EQU DPRBASE+$0008 ; Transmit Buffer Discriptor address REGB EQU DPRBASE+$1000 ; Base address of Internal Registers SCC1PB EQU DPRBASE+$0C00 ; SCC1 Protocol Base address SCC2PB EQU DPRBASE+$0D00 ; SCC2 Protocol Base address SCC3PB EQU DPRBASE+$0E00 ; SCC3 Protocol Base address SCC4PB EQU DPRBASE+$0F00 ; SCC4 Protocol Base address SPIPB EQU DPRBASE+$0D80 ; SPI Protocol Base SMC1PB EQU DPRBASE+$0E80 ; SMC1 Protocol Base SMC2PB EQU DPRBASE+$0F80 ; SMC2 Protocol Base IDMA1PB EQU DPRBASE+$0E70 ; IDMA1 Protocol Base IDMA2PB EQU DPRBASE+$0F70 ; IDMA2 Protocol Base ************************ SIM Module registers MCR EQU REGB+$0000 ; Module Configuration AVR EQU REGB+$0008 ; Auto Vector RSR EQU REGB+$0009 ; Reset Status CLKOCR EQU REGB+$000C ; CLKO Control PPLCR EQU REGB+$0010 ; PPL Control CDVCR EQU REGB+$0014 ; Clock Divider Control * PEPAR EQU REGB+$0016 ; Port E Pin Assignment * SYPCR EQU REGB+$0022 ; System Protection Control SWIV EQU REGB+$0023 ; S/w Interrupt Vector PICR EQU REGB+$0026 ; Periodic Interrupt Control PITR EQU REGB+$002A ; Periodic Interrupt Timing SWSR EQU REGB+$002F ; S/w Service BKAR EQU REGB+$0032 ; Breakpoint Address BKCQ EQU REGB+$0034 ; Breakpoint Control * GMR EQU REGB+$0040 ; Global Memory MSTAT EQU REGB+$0044 ; MEMC Status * BR0 EQU REGB+$0050 ; Base Register 0 OR0 EQU REGB+$0054 ; Option Register 0 BR1 EQU REGB+$0060 ; Base Register 1 OR1 EQU REGB+$0064 ; Option Register 1 BR2 EQU REGB+$0070 ; Base Register 2 OR2 EQU REGB+$0074 ; Option Register 2 BR3 EQU REGB+$0080 ; Base Register 3 OR3 EQU REGB+$0084 ; Option Register 3 BR4 EQU REGB+$0090 ; Base Register 4 OR4 EQU REGB+$0094 ; Option Register 4 BR5 EQU REGB+$00A0 ; Base Register 5 OR5 EQU REGB+$00A4 ; Option Register 5 BR6 EQU REGB+$00B0 ; Base Register 6 OR6 EQU REGB+$00B4 ; Option Register 6 BR7 EQU REGB+$00C0 ; Base Register 7 OR7 EQU REGB+$00C4 ; Option Register 7 * ************************ CPM Module registers ******************* * ICCR EQU REGB+$0500 ; Channel Configuration *** IDMA1, 2 CMR1 EQU REGB+$0504 ; IDMA1 Mode SAPR1 EQU REGB+$0508 ; IDMA1 Source Address Pointer DAPR1 EQU REGB+$050C ; IDMA1 destination Address Pointer BCR1 EQU REGB+$0510 ; IDMA1 Byte Count FCR1 EQU REGB+$0514 ; IDMA1 Fuction Code CMAR1 EQU REGB+$0516 ; IDMA1 Channel Mask CSR1 EQU REGB+$0518 ; IDMA1 Channel Status * CMR2 EQU REGB+$0526 ; IDMA2 Mode SAPR2 EQU REGB+$0528 ; IDMA2 Source Address Pointer DAPR2 EQU REGB+$052C ; IDMA2 destination Address Pointer BCR2 EQU REGB+$0530 ; IDMA2 Byte Count FCR2 EQU REGB+$0534 ; IDMA2 Fuction Code CMAR2 EQU REGB+$0536 ; IDMA2 Channel Mask CSR2 EQU REGB+$0538 ; IDMA2 Channel Status *** SDMA SDSR EQU REGB+$051C ; SDMA Status SDCR EQU REGB+$051E ; SDMA Configuration Register SDAR EQU REGB+$0520 ; SDMA Address Register *** CP Interrupt CICR EQU REGB+$0540 ; CP Interrupt Configuration CIPR EQU REGB+$0544 ; CP Interrupt Pending CIMR EQU REGB+$0548 ; CP Interrupt Mask CISR EQU REGB+$054C ; CP Interrupt In-service *** Port A, B, C PADIR EQU REGB+$0550 ; Port A Data Direction Assignment PAPAR EQU REGB+$0552 ; Port A Pin Function Assignment PAODR EQU REGB+$0554 ; Port A Open Drain Assignment PADAT EQU REGB+$0556 ; Port A Data Content * PBDIR EQU REGB+$06B8 ; Port B Data Direction Assignment PBPAR EQU REGB+$06BC ; Port B Pin Function Assignment PBODR EQU REGB+$06C0 ; Port B Open Drain Assignment PBDAT EQU REGB+$06C4 ; Port B Data Content * PCDIR EQU REGB+$0560 ; Port C Data Direction Assignment PCPAR EQU REGB+$0562 ; Port C Pin Assignment PCSO EQU REGB+$0564 ; Port C Special Options PCDAT EQU REGB+$0566 ; Port C Data Content PCINT EQU REGB+$0568 ; Port C Interrupt Control *** Timer 1, 2, 3, 4 TGCR EQU REGB+$0580 ; Timer Global Configuration * TMR1 EQU REGB+$0590 ; Timer1 Mode TMR2 EQU REGB+$0592 ; Timer2 Mode TRR1 EQU REGB+$0594 ; Timer1 Reference TRR2 EQU REGB+$0596 ; Timer2 Reference TCR1 EQU REGB+$0598 ; Timer1 Capture TCR2 EQU REGB+$059A ; Timer2 Capture TCN1 EQU REGB+$059C ; Timer1 Counter TCN2 EQU REGB+$059E ; Timer2 Counter * TMR3 EQU REGB+$05A0 ; Timer3 Mode TMR4 EQU REGB+$05A2 ; Timer4 Mode TRR3 EQU REGB+$05A4 ; Timer3 Reference TRR4 EQU REGB+$05A6 ; Timer4 Reference TCR3 EQU REGB+$05A8 ; Timer3 Capture TCR4 EQU REGB+$05AA ; Timer4 Capture TCN3 EQU REGB+$05AC ; Timer3 Counter TCN4 EQU REGB+$05AE ; Timer4 Counter * TER1 EQU REGB+$05B0 ; Timer1 Event TER2 EQU REGB+$05B2 ; Timer2 Event TER3 EQU REGB+$05B4 ; Timer3 Event TER4 EQU REGB+$05B6 ; Timer4 Event *** CP CR EQU REGB+$05C0 ; CP Command RCCR EQU REGB+$05C4 ; RISC Configuration RTER EQU REGB+$05D6 ; RISC Timer Event Register RTMR EQU REGB+$05DA ; RISC Timer Mask Register * BRG 1, 2, 3, 4 BRGC1 EQU REGB+$05F0 ; BRG1 Configuration BRGC2 EQU REGB+$05F4 ; BRG2 Configuration BRGC3 EQU REGB+$05F8 ; BRG3 Configuration BRGC4 EQU REGB+$05FC ; BRG4 Configuration *** SCC 1, 2, 3, 4 * SCC1 GSMR_L1 EQU REGB+$0600 ; SCC1 General Mode GSMR_H1 EQU REGB+$0604 ; SCC1 General Mode PSMR1 EQU REGB+$0608 ; SCC1 Protocol Specific Mode TODR1 EQU REGB+$060C ; SCC1 Transmit On Demand DSR1 EQU REGB+$060E ; SCC1 Data Sync SCCE1 EQU REGB+$0610 ; SCC1 Event SCCM1 EQU REGB+$0614 ; SCC1 Mask SCCS1 EQU REGB+$0617 ; SCC1 Status * SCC2 GSMR_L2 EQU REGB+$0620 ; SCC2 General Mode GSMR_H2 EQU REGB+$0624 ; SCC2 General Mode PSMR2 EQU REGB+$0628 ; SCC2 Protocol Specific Mode TODR2 EQU REGB+$062C ; SCC2 Transmit On Demand DSR2 EQU REGB+$062E ; SCC2 Data Sync SCCE2 EQU REGB+$0630 ; SCC2 Event SCCM2 EQU REGB+$0634 ; SCC2 Mask SCCS2 EQU REGB+$0637 ; SCC2 Status * SCC3 GSMR_L3 EQU REGB+$0640 ; SCC3 General Mode GSMR_H3 EQU REGB+$0644 ; SCC3 General Mode PSMR3 EQU REGB+$0648 ; SCC3 Protocol Specific Mode TODR3 EQU REGB+$064C ; SCC3 Transmit On Demand DSR3 EQU REGB+$064E ; SCC3 Data Sync SCCE3 EQU REGB+$0650 ; SCC3 Event SCCM3 EQU REGB+$0654 ; SCC3 Mask SCCS3 EQU REGB+$0657 ; SCC3 Status * SCC4 GSMR_L4 EQU REGB+$0660 ; SCC4 General Mode GSMR_H4 EQU REGB+$0664 ; SCC4 General Mode PSMR4 EQU REGB+$0668 ; SCC4 Protocol Specific Mode TODR4 EQU REGB+$066C ; SCC4 Transmit On Demand DSR4 EQU REGB+$066E ; SCC4 Data Sync SCCE4 EQU REGB+$0670 ; SCC4 Event SCCM4 EQU REGB+$0674 ; SCC4 Mask SCCS4 EQU REGB+$0677 ; SCC4 Status *** SMC 1, 2 SMCMR1 EQU REGB+$0682 ; SMC1 Mode SMCE1 EQU REGB+$0686 ; SMC1 Event SMCM1 EQU REGB+$068A ; SMC1 Mask * SMCMR2 EQU REGB+$0692 ; SMC2 Mode SMCE2 EQU REGB+$0696 ; SMC2 Event SMCM2 EQU REGB+$069A ; SMC2 Mask *** SPI SPMODE EQU REGB+$06A0 ; SPI Mode SPIE EQU REGB+$06A6 ; SPI Event SPIM EQU REGB+$06AA ; SPI Mask SPCOM EQU REGB+$06AD ; SPI Command *** PIP PIPC EQU REGB+$06B2 ; PIP Configuration PTRR EQU REGB+$06B6 ; PIP Timing Parameter *** Serial Interface SIMODE EQU REGB+$06E0 ; SI Mode SIGMR EQU REGB+$06E4 ; SI Global Mode SISTR EQU REGB+$06E6 ; SI Status SICMR EQU REGB+$06E7 ; SI Command SICR EQU REGB+$06EC ; SI Clock Routing SIRP EQU REGB+$06F0 ; SI RAM Pointer SIRAM EQU REGB+$0700 ; SI Routing RAM ************************ END of SIM/CPM Register MAP ************************ SCC Parameters ****** SCC1 RBASE1 EQU SCC1PB+$000 ; SCC1 RX BD Base Address TBASE1 EQU SCC1PB+$002 ; SCC1 TX BD Base Address RFCR1 EQU SCC1PB+$004 ; SCC1 RX Function Code TFCR1 EQU SCC1PB+$005 ; SCC1 TX Function Code MRBLR1 EQU SCC1PB+$006 ; SCC1 MAX Buffer Length - RX RSTATE1 EQU SCC1PB+$008 ; SCC1 RX Internal State RBPRT1 EQU SCC1PB+$010 ; SCC1 RX BD Pointer TSTATE1 EQU SCC1PB+$018 ; SCC1 TX Internal State TBPRT1 EQU SCC1PB+$020 ; SCC1 TX BD Pointer RCRC1 EQU SCC1PB+$028 ; SCC1 Temp Receive CRC TCRC1 EQU SCC1PB+$02C ; SCC1 Temp Transmit CRC ****** SCC2 RBASE2 EQU SCC2PB+$000 ; SCC2 RX BD Base Address TBASE2 EQU SCC2PB+$002 ; SCC2 TX BD Base Address RFCR2 EQU SCC2PB+$004 ; SCC2 RX Function Code TFCR2 EQU SCC2PB+$005 ; SCC2 TX Function Code MRBLR2 EQU SCC2PB+$006 ; SCC2 MAX Buffer Length - RX RSTATE2 EQU SCC2PB+$008 ; SCC2 RX Internal State RBPRT2 EQU SCC2PB+$010 ; SCC2 RX BD Pointer TSTATE2 EQU SCC2PB+$018 ; SCC2 TX Internal State TBPRT2 EQU SCC2PB+$020 ; SCC2 TX BD Pointer RCRC2 EQU SCC2PB+$028 ; SCC2 Temp Receive CRC TCRC2 EQU SCC2PB+$02C ; SCC2 Temp Transmit CRC ****** SCC3 RBASE3 EQU SCC3PB+$000 ; SCC3 RX BD Base Address TBASE3 EQU SCC3PB+$002 ; SCC3 TX BD Base Address RFCR3 EQU SCC3PB+$004 ; SCC3 RX Function Code TFCR3 EQU SCC3PB+$005 ; SCC3 TX Function Code MRBLR3 EQU SCC3PB+$006 ; SCC3 MAX Buffer Length - RX RSTATE3 EQU SCC3PB+$008 ; SCC3 RX Internal State RBPRT3 EQU SCC3PB+$010 ; SCC3 RX BD Pointer TSTATE3 EQU SCC3PB+$018 ; SCC3 TX Internal State TBPRT3 EQU SCC3PB+$020 ; SCC3 TX BD Pointer RCRC3 EQU SCC3PB+$028 ; SCC3 Temp Receive CRC TCRC3 EQU SCC3PB+$02C ; SCC3 Temp Transmit CRC ****** SCC4 RBASE4 EQU SCC4PB+$000 ; SCC4 RX BD Base Address TBASE4 EQU SCC4PB+$002 ; SCC4 TX BD Base Address RFCR4 EQU SCC4PB+$004 ; SCC4 RX Function Code TFCR4 EQU SCC4PB+$005 ; SCC4 TX Function Code MRBLR4 EQU SCC4PB+$006 ; SCC4 MAX Buffer Length - RX RSTATE4 EQU SCC4PB+$008 ; SCC4 RX Internal State RBPRT4 EQU SCC4PB+$010 ; SCC4 RX BD Pointer TSTATE4 EQU SCC4PB+$018 ; SCC4 TX Internal State TBPRT4 EQU SCC4PB+$020 ; SCC4 TX BD Pointer RCRC4 EQU SCC4PB+$028 ; SCC4 Temp Receive CRC TCRC4 EQU SCC4PB+$02C ; SCC4 Temp Transmit CRC CRC_C4 EQU SCC4PB+$030 ; SCC4 CRC Constant Total-Transparent CRC_P4 EQU SCC4PB+$034 ; SCC4 CRC Preset Total-Transparent ****** SMC1 => SMCA, simplify assembly coding RBASEA EQU SMC1PB+$000 ; SMC1 RX BD Base Address TBASEA EQU SMC1PB+$002 ; SMC1 TX BD Base Address RFCRA EQU SMC1PB+$004 ; SMC1 RX Function Code TFCRA EQU SMC1PB+$005 ; SMC1 TX Function Code MRBLRA EQU SMC1PB+$006 ; SMC1 MAX Buffer Length - RX RSTATEA EQU SMC1PB+$008 ; SMC1 RX Internal State RBPRTA EQU SMC1PB+$010 ; SMC1 RX BD Pointer TSTATEA EQU SMC1PB+$018 ; SMC1 TX Internal State TBPRTA EQU SMC1PB+$020 ; SMC1 TX BD Pointer ****** SMC1 => SMCB RBASEB EQU SMC2PB+$000 ; SMC2 RX BD Base Address TBASEB EQU SMC2PB+$002 ; SMC2 TX BD Base Address RFCRB EQU SMC2PB+$004 ; SMC2 RX Function Code TFCRB EQU SMC2PB+$005 ; SMC2 TX Function Code MRBLRB EQU SMC2PB+$006 ; SMC2 MAX Buffer Length - RX RSTATEB EQU SMC2PB+$008 ; SMC2 RX Internal State RBPRTB EQU SMC2PB+$010 ; SMC2 RX BD Pointer TSTATEB EQU SMC2PB+$018 ; SMC2 TX Internal State TBPRTB EQU SMC2PB+$020 ; SMC2 TX BD Pointer ************************** Specific Parameters * SCC1, Ethernet Specific Parameter C_PRES1 EQU SCC1PB+$34 ; SCC1 Preset CRC ($FFFFFFFF) C_MASK1 EQU SCC1PB+$30 ; SCC1 Constant mask for CRC($20E3DEBB) CRCEC1 EQU SCC1PB+$38 ; SCC1 CRC error counter ALEC1 EQU SCC1PB+$3C ; SCC1 alignment error counter DISFC1 EQU SCC1PB+$40 ; SCC1 discard frame counter PADS1 EQU SCC1PB+$44 ; SCC1 short frame PAD counter RET_Lim1 EQU SCC1PB+$46 ; SCC1 retry limit threshold RET_cnt1 EQU SCC1PB+$48 ; SCC1 retry limit counter MFLR1 EQU SCC1PB+$4A ; SCC1 max. frame length reg. MINFLR1 EQU SCC1PB+$4C ; SCC1 min. frame length reg. MAXD11 EQU SCC1PB+$4E ; SCC1 max. DMA1 length reg. MAXD21 EQU SCC1PB+$50 ; SCC1 max. DMA2 length reg. MAXD1 EQU SCC1PB+$52 ; SCC1 Rx max DMA DMA_cnt1 EQU SCC1PB+$54 ; SCC1 Rx DMA count MAX_b1 EQU SCC1PB+$56 ; SCC1 max BD byte count GADDR11 EQU SCC1PB+$58 ; SCC1 Group Addr. Filter 1 GADDR21 EQU SCC1PB+$5A ; SCC1 Group Addr. Filter 2 GADDR31 EQU SCC1PB+$5C ; SCC1 Group Addr. Filter 3 GADDR41 EQU SCC1PB+$5E ; SCC1 Group Addr. Filter 4 TBUF0.data01 EQU SCC1PB+$60 ; SCC1 save area 0 - current frame TBUF0.data11 EQU SCC1PB+$64 ; SCC1 save area 1 - current frame TBUF0.rba01 EQU SCC1PB+$68 ; SCC1 TBUF0.crc1 EQU SCC1PB+$6C ; SCC1 TBUF0.bcnt1 EQU SCC1PB+$70 ; SCC1 PADDR1_H1 EQU SCC1PB+$72 ; physical address 1 (MSB) PADDR1_M1 EQU SCC1PB+$74 ; physical address 1 PADDR1_L1 EQU SCC1PB+$76 ; physical address 1 (LSB) P_PER1 EQU SCC1PB+$78 ; persistence RFBD_ptr1 EQU SCC1PB+$7A ; Rx first BD pointer TFBD_ptr1 EQU SCC1PB+$7C ; Tx first BD pointer TLBD_ptr1 EQU SCC1PB+$7E ; Tx last BD pointer TBUF1.data01 EQU SCC1PB+$80 ; SCC1 save area 0 - next frame TBUF1.data11 EQU SCC1PB+$84 ; SCC1 save area 1 - next frame TBUF1.rba01 EQU SCC1PB+$88 ; SCC1 TBUF1.crc1 EQU SCC1PB+$8C ; SCC1 TBUF1.bcnt1 EQU SCC1PB+$90 ; SCC1 TX_len1 EQU SCC1PB+$92 ; SCC1 Tx frame length counter IADDR11 EQU SCC1PB+$94 ; SCC1 Individual Addr. Filter 1 IADDR21 EQU SCC1PB+$96 ; SCC1 Individual Addr. Filter 2 IADDR31 EQU SCC1PB+$98 ; SCC1 Individual Addr. Filter 3 IADDR41 EQU SCC1PB+$9A ; SCC1 Individual Addr. Filter 4 BOFF_CNT1 EQU SCC1PB+$9C ; back off counter TADDR1_H1 EQU SCC1PB+$9E ; temp address (MSB) TADDR1_M1 EQU SCC1PB+$A0 ; temp address TADDR1_L1 EQU SCC1PB+$A2 ; temp address (LSB) * SCC2, HDLC Specific Parameters C_MASK2 EQU SCC2PB+$34 ; SCC2 CRC Constant C_PRES2 EQU SCC2PB+$38 ; SCC2 CRC Preset DISFC2 EQU SCC2PB+$3C ; SCC2 Discard Frame Counter CRCEC2 EQU SCC2PB+$3E ; SCC2 CRC Error Counter ABTSC2 EQU SCC2PB+$40 ; SCC2 Abort Sequence Counter NMARC2 EQU SCC2PB+$42 ; SCC2 NonMatch Addr Rx Counter RETRC2 EQU SCC2PB+$44 ; SCC2 Frame ReTRansmit Counter MFLR2 EQU SCC2PB+$46 ; SCC2 Max Frame Length Register MAXCNT2 EQU SCC2PB+$48 ; SCC2 MAX length Counter RFTHR2 EQU SCC2PB+$4A ; SCC2 Receive Frames THreshold RFCNT2 EQU SCC2PB+$4C ; SCC2 Receive Frames Count HMASK2 EQU SCC2PB+$4E ; SCC2 Frame Address Mask (U-D) HADDR12 EQU SCC2PB+$50 ; SCC2 Frame Address 1 HADDR22 EQU SCC2PB+$52 ; SCC2 Frame Address 2 HADDR32 EQU SCC2PB+$54 ; SCC2 Frame Address 3 HADDR42 EQU SCC2PB+$56 ; SCC2 Frame Address 4 * SCC4, HDLC Specific Parameters C_MASK4 EQU SCC4PB+$34 ; SCC4 CRC Constant C_PRES4 EQU SCC4PB+$38 ; SCC4 CRC Preset DISFC4 EQU SCC4PB+$3C ; SCC4 Discard Frame Counter CRCEC4 EQU SCC4PB+$3E ; SCC4 CRC Error Counter ABTSC4 EQU SCC4PB+$40 ; SCC4 Abort Sequence Counter NMARC4 EQU SCC4PB+$42 ; SCC4 NonMatch Addr Rx Counter RETRC4 EQU SCC4PB+$44 ; SCC4 Frame ReTRansmit Counter MFLR4 EQU SCC4PB+$46 ; SCC4 Max Frame Length Register MAXCNT4 EQU SCC4PB+$48 ; SCC4 MAX length Counter RFTHR4 EQU SCC4PB+$4A ; SCC4 Receive Frames THreshold RFCNT4 EQU SCC4PB+$4C ; SCC4 Receive Frames Count HMASK4 EQU SCC4PB+$4E ; SCC4 Frame Address Mask (U-D) HADDR14 EQU SCC4PB+$50 ; SCC4 Frame Address 1 HADDR24 EQU SCC4PB+$52 ; SCC4 Frame Address 2 HADDR34 EQU SCC4PB+$54 ; SCC4 Frame Address 3 HADDR44 EQU SCC4PB+$56 ; SCC4 Frame Address 4 * SCC4, UART Specific Parameters MAXIDL4 EQU SCC4PB+$38 ; SCC4 MAX IDLe cchars IDLC4 EQU SCC4PB+$3A ; SCC4 temp IDLe Counter BRKCR4 EQU SCC4PB+$3C ; SCC4 BReaK Count Register (TX) PAREC4 EQU SCC4PB+$3E ; SCC4 Parity Error Counter (RX) FRMER4 EQU SCC4PB+$40 ; SCC4 Framing Error Counter (RX) NOSEC4 EQU SCC4PB+$42 ; SCC4 Noise Counter (RX) BRKEC4 EQU SCC4PB+$44 ; SCC4 BReaK Condition Counter (RX) BRKLN4 EQU SCC4PB+$46 ; SCC4 Last BReaK Length (RX) UADDR14 EQU SCC4PB+$48 ; SCC4 UART Address Character 1 UADDR24 EQU SCC4PB+$4A ; SCC4 UART Address Character 2 RETMP4 EQU SCC4PB+$4C ; SCC4 Temp storage TOSEQ4 EQU SCC4PB+$4E ; SCC4 TX out of sequence Character CCHAR14 EQU SCC4PB+$50 ; SCC4 Control Character 1 CCHAR24 EQU SCC4PB+$52 ; SCC4 Control Character 2 CCHAR34 EQU SCC4PB+$54 ; SCC4 Control Character 3 CCHAR44 EQU SCC4PB+$56 ; SCC4 Control Character 4 CCHAR54 EQU SCC4PB+$58 ; SCC4 Control Character 5 CCHAR64 EQU SCC4PB+$5A ; SCC4 Control Character 6 CCHAR74 EQU SCC4PB+$5C ; SCC4 Control Character 7 CCHAR84 EQU SCC4PB+$5E ; SCC4 Control Character 8 RCCM4 EQU SCC4PB+$60 ; SCC4 RX Control Character Mask RCCR4 EQU SCC4PB+$62 ; SCC4 RX Control Character RLBC4 EQU SCC4PB+$64 ; SCC4 RX Last Break Character * SCC3, BISYNC Specific Parameters CRCC3 EQU SCC3PB+$38 ; SCC3 CRC Constant Temp Value PRCRC3 EQU SCC3PB+$3A ; SCC3 Preset RX CRC16/LRC PTCRC3 EQU SCC3PB+$3C ; SCC3 Preset TX CRC16/LRC PAREC3 EQU SCC3PB+$3E ; SCC3 Parity Error Counter (RX) BSYNC3 EQU SCC3PB+$40 ; SCC3 BISYNC SYNC Character BIDLE3 EQU SCC3PB+$42 ; SCC3 BISYNC IDLE Character CCHAR13 EQU SCC3PB+$44 ; SCC3 Control Character 1 CCHAR23 EQU SCC3PB+$46 ; SCC3 Control Character 2 CCHAR33 EQU SCC3PB+$48 ; SCC3 Control Character 3 CCHAR43 EQU SCC3PB+$4A ; SCC3 Control Character 4 CCHAR53 EQU SCC3PB+$4C ; SCC3 Control Character 5 CCHAR63 EQU SCC3PB+$4E ; SCC3 Control Character 6 CCHAR73 EQU SCC3PB+$50 ; SCC3 Control Character 7 CCHAR83 EQU SCC3PB+$52 ; SCC3 Control Character 8 RCCM3 EQU SCC3PB+$54 ; SCC3 RX Control Character Mask * SMC1, UART Specific Parameters MAXIDLA EQU SMC1PB+$28 ; SMC1 MAX IDLe cchars IDLCA EQU SMC1PB+$2A ; SMC1 temp IDLe Counter BRKLA EQU SMC1PB+$2C ; SMC1 last Received BReaK char length BRKECA EQU SMC1PB+$2E ; SMC1 receive BReaK Condition Counter BRKCRA EQU SMC1PB+$30 ; SMC1 BReaK Count Register (TX) ORG INIT MOVE.W #$0303,PAPAR ; port A pin 1+2+8+9 - dedicated function (RXD,TXD,CLK1+2) MOVE.W #$0000,PADIR ; all port A pins inputs MOVE.W #$0000,PCPAR ; port C select RTS1(TENA),CTS1(CLSN),CD1(RENA) * ; but do not enable TENA jet $0001 CLR.W PCDIR MOVE.W #$0030,PCSO ; port C CTS1(CLSN) and CD1 (RENA) MOVE.W #$0750,SDCR ; Interrupt service mask = 7 and arbit. ID = 5 * this example is running in normal mode, but you can also use it in loopback * for loopback mode take the '*' lines and comment out the related once. MOVE.L #$00000024,SICR ; route CLK1+2 to SCC1 and select NMSI pins * MOVE.L #$00010002,BRGC2 ; if you want to use loopback mode, you have * MOVE.L #$00000009,SICR ; generate an ext. clock. BRGC2 is generating * ; a clock and this clk is routed to RCLK and * ; TCLK of SCC1. MOVE.W #$0000,RBASE1 ; receive buffer dis. MOVE.W #$0008,TBASE1 ; trans. buffer dis. MOVE.B #$15,RFCR1 ; normal mode for receive MOVE.B #$15,TFCR1 ; normal mode for trans. MOVE.W #$05F0,MRBLR4 ; max. bytes per receiver (1520) MOVE.W #$0001,CR ; initalize transmit and receive parameter of SCC1 MOVE.L #$DEBB20E3,C_MASK1 ; 32 Bit CCITT CRC MOVE.L #$FFFFFFFF,C_PRES1 ; 32 Bit CCITT CRC MOVE.L #$0,CRCEC1 MOVE.L #$0,ALEC1 MOVE.L #$0,DISFC1 MOVE.W #$8888,PADS1 MOVE.W #$000F,RET_Lim1 MOVE.W #$05EE,MFLR1 MOVE.W #$0040,MINFLR1 MOVE.W #$05EE,MAXD11 MOVE.W #$05EE,MAXD21 MOVE.W #$05EE,DMA_cnt1 MOVE.W #$0,GADDR11 MOVE.W #$0,GADDR21 MOVE.W #$0,GADDR31 MOVE.W #$0,GADDR41 MOVE.W #$0000,PADDR1_H1 MOVE.W #$0000,PADDR1_M1 MOVE.W #$0040,PADDR1_L1 MOVE.W #$0000,P_PER1 MOVE.W #$0,IADDR11 MOVE.W #$0,IADDR21 MOVE.W #$0,IADDR31 MOVE.W #$0,IADDR41 MOVE.W #$0,TADDR1_H1 MOVE.W #$0,TADDR1_M1 MOVE.W #$0,TADDR1_L1 MOVE.W #$B000,RXBD+$0000 ; RxBD status reg. MOVE.W #$0000,RXBD+$0002 ; data length reg. MOVE.L #$00404000,RXBD+$0004 ; pointer to data at $404000 MOVE.W #$FC00,TXBD+$0000 ; TxBD status reg. MOVE.W #$000D,TXBD+$0002 ; data length reg. MOVE.L #$00404100,TXBD+$0004 ; pointer to data at $404100 MOVE.W #$FFFF,SCCE1 ; clears all pending events of SCC1 MOVE.W #$001A,SCCM1 ; enable TXE, RXF and TXB interrupts * the next two lines would let the SCC1 generate an interrupt to the system. * don't forget to clear the interrupt pending register, if you use this option. * MOVE.L #$00E44000,CICR ; interrupt configuraton reg. * MOVE.L #$40000000,CIMR ; allow SCC1 a system interrupt MOVE.L #$00000000,GSMR_H1 * MOVE.L #$1088004C,GSMR_L1 ; SCC1 conf. reg. set to automatic * ; control of CLSN and RENA, more setup * ; time for the EEST, loopback and ethernet mode. * ; ENR and ENT are not enabled jet. MOVE.L #$1088000C,GSMR_L1 ; SCC1 conf. reg. set to automatic * ; control of CLSN and RENA, more setup * ; time for the EEST and ethernet mode. * ; ENR and ENT are not enabled jet. * MOVE.W #$2A4A,PSMR1 ; ethernet mode reg. is set to receive * ; short frames, 32 bit CRC, reject all frames, * ; loop operation and begin searching for the * ; start frame delimiter 22 bits after RENA MOVE.W #$2A4A,PSMR1 ; ethernet mode reg. is set to receive * ; short frames, 32 bit CRC, reject all frames, * ; and begin searching for the * ; start frame delimiter 22 bits after RENA MOVE.W #$D555,DSR1 MOVE.W #$D555,DSR1 MOVE.W #$0001,PCPAR ; enable TENA * MOVE.L #$1088007C,GSMR_L1 ; enable transmitter in loopback mode MOVE.L #$1088003C,GSMR_L1 ; enable transmitter in normal mode END