as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 1 Source file: ethn_ex1.asm 1 0 | * 2 0 | * Header File for the QUICC ( MC68360 ) 3 0 | * Ethernet Example User's Manual Page 7-272 4 0 | * PH 5/5/93 5 0 | ************************************************************* 6 0 | * 7 0 [$402000] | INIT EQU $0402000 ; QUADS Board DRAM User Space 8 0 | * 9 0 | ************************** DUAL PORT RAM 10 0 [$3FF00] | MBAR EQU $03FF00 ; Module Base Address, (MBAR)=REGB 11 0 [$3FF08] | MBARE EQU $03FF08 ; Module Base Address Enable SLAVE 12 0 | * 13 0 [$20000] | DPRBASE EQU $00020000 ; Base address of dual-port RAM 14 0 [$20000] | RXBD EQU DPRBASE+$0000 ; Receive Buffer Discriptor address 15 0 [$20008] | TXBD EQU DPRBASE+$0008 ; Transmit Buffer Discriptor address 16 0 [$21000] | REGB EQU DPRBASE+$1000 ; Base address of Internal Registers 17 0 [$20C00] | SCC1PB EQU DPRBASE+$0C00 ; SCC1 Protocol Base address 18 0 [$20D00] | SCC2PB EQU DPRBASE+$0D00 ; SCC2 Protocol Base address 19 0 [$20E00] | SCC3PB EQU DPRBASE+$0E00 ; SCC3 Protocol Base address 20 0 [$20F00] | SCC4PB EQU DPRBASE+$0F00 ; SCC4 Protocol Base address 21 0 [$20D80] | SPIPB EQU DPRBASE+$0D80 ; SPI Protocol Base 22 0 [$20E80] | SMC1PB EQU DPRBASE+$0E80 ; SMC1 Protocol Base 23 0 [$20F80] | SMC2PB EQU DPRBASE+$0F80 ; SMC2 Protocol Base 24 0 [$20E70] | IDMA1PB EQU DPRBASE+$0E70 ; IDMA1 Protocol Base 25 0 [$20F70] | IDMA2PB EQU DPRBASE+$0F70 ; IDMA2 Protocol Base 26 0 | 27 0 | ************************ SIM Module registers 28 0 | 29 0 [$21000] | MCR EQU REGB+$0000 ; Module Configuration 30 0 [$21008] | AVR EQU REGB+$0008 ; Auto Vector 31 0 [$21009] | RSR EQU REGB+$0009 ; Reset Status 32 0 [$2100C] | CLKOCR EQU REGB+$000C ; CLKO Control 33 0 [$21010] | PPLCR EQU REGB+$0010 ; PPL Control 34 0 [$21014] | CDVCR EQU REGB+$0014 ; Clock Divider Control 35 0 | * 36 0 [$21016] | PEPAR EQU REGB+$0016 ; Port E Pin Assignment 37 0 | * 38 0 [$21022] | SYPCR EQU REGB+$0022 ; System Protection Control 39 0 [$21023] | SWIV EQU REGB+$0023 ; S/w Interrupt Vector 40 0 [$21026] | PICR EQU REGB+$0026 ; Periodic Interrupt Control 41 0 [$2102A] | PITR EQU REGB+$002A ; Periodic Interrupt Timing 42 0 [$2102F] | SWSR EQU REGB+$002F ; S/w Service 43 0 [$21032] | BKAR EQU REGB+$0032 ; Breakpoint Address 44 0 [$21034] | BKCQ EQU REGB+$0034 ; Breakpoint Control 45 0 | * 46 0 [$21040] | GMR EQU REGB+$0040 ; Global Memory 47 0 [$21044] | MSTAT EQU REGB+$0044 ; MEMC Status 48 0 | * 49 0 [$21050] | BR0 EQU REGB+$0050 ; Base Register 0 50 0 [$21054] | OR0 EQU REGB+$0054 ; Option Register 0 51 0 [$21060] | BR1 EQU REGB+$0060 ; Base Register 1 52 0 [$21064] | OR1 EQU REGB+$0064 ; Option Register 1 53 0 [$21070] | BR2 EQU REGB+$0070 ; Base Register 2 54 0 [$21074] | OR2 EQU REGB+$0074 ; Option Register 2 55 0 [$21080] | BR3 EQU REGB+$0080 ; Base Register 3 as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 2 Source file: ethn_ex1.asm 56 0 [$21084] | OR3 EQU REGB+$0084 ; Option Register 3 57 0 [$21090] | BR4 EQU REGB+$0090 ; Base Register 4 58 0 [$21094] | OR4 EQU REGB+$0094 ; Option Register 4 59 0 [$210A0] | BR5 EQU REGB+$00A0 ; Base Register 5 60 0 [$210A4] | OR5 EQU REGB+$00A4 ; Option Register 5 61 0 [$210B0] | BR6 EQU REGB+$00B0 ; Base Register 6 62 0 [$210B4] | OR6 EQU REGB+$00B4 ; Option Register 6 63 0 [$210C0] | BR7 EQU REGB+$00C0 ; Base Register 7 64 0 [$210C4] | OR7 EQU REGB+$00C4 ; Option Register 7 65 0 | * 66 0 | ************************ CPM Module registers ******************* 67 0 | * 68 0 [$21500] | ICCR EQU REGB+$0500 ; Channel Configuration 69 0 | *** IDMA1, 2 70 0 [$21504] | CMR1 EQU REGB+$0504 ; IDMA1 Mode 71 0 [$21508] | SAPR1 EQU REGB+$0508 ; IDMA1 Source Address Pointer 72 0 [$2150C] | DAPR1 EQU REGB+$050C ; IDMA1 destination Address Pointer 73 0 [$21510] | BCR1 EQU REGB+$0510 ; IDMA1 Byte Count 74 0 [$21514] | FCR1 EQU REGB+$0514 ; IDMA1 Fuction Code 75 0 [$21516] | CMAR1 EQU REGB+$0516 ; IDMA1 Channel Mask 76 0 [$21518] | CSR1 EQU REGB+$0518 ; IDMA1 Channel Status 77 0 | * 78 0 [$21526] | CMR2 EQU REGB+$0526 ; IDMA2 Mode 79 0 [$21528] | SAPR2 EQU REGB+$0528 ; IDMA2 Source Address Pointer 80 0 [$2152C] | DAPR2 EQU REGB+$052C ; IDMA2 destination Address Pointer 81 0 [$21530] | BCR2 EQU REGB+$0530 ; IDMA2 Byte Count 82 0 [$21534] | FCR2 EQU REGB+$0534 ; IDMA2 Fuction Code 83 0 [$21536] | CMAR2 EQU REGB+$0536 ; IDMA2 Channel Mask 84 0 [$21538] | CSR2 EQU REGB+$0538 ; IDMA2 Channel Status 85 0 | *** SDMA 86 0 [$2151C] | SDSR EQU REGB+$051C ; SDMA Status 87 0 [$2151E] | SDCR EQU REGB+$051E ; SDMA Configuration Register 88 0 [$21520] | SDAR EQU REGB+$0520 ; SDMA Address Register 89 0 | *** CP Interrupt 90 0 [$21540] | CICR EQU REGB+$0540 ; CP Interrupt Configuration 91 0 [$21544] | CIPR EQU REGB+$0544 ; CP Interrupt Pending 92 0 [$21548] | CIMR EQU REGB+$0548 ; CP Interrupt Mask 93 0 [$2154C] | CISR EQU REGB+$054C ; CP Interrupt In-service 94 0 | *** Port A, B, C 95 0 [$21550] | PADIR EQU REGB+$0550 ; Port A Data Direction Assignment 96 0 [$21552] | PAPAR EQU REGB+$0552 ; Port A Pin Function Assignment 97 0 [$21554] | PAODR EQU REGB+$0554 ; Port A Open Drain Assignment 98 0 [$21556] | PADAT EQU REGB+$0556 ; Port A Data Content 99 0 | * 100 0 [$216B8] | PBDIR EQU REGB+$06B8 ; Port B Data Direction Assignment 101 0 [$216BC] | PBPAR EQU REGB+$06BC ; Port B Pin Function Assignment 102 0 [$216C0] | PBODR EQU REGB+$06C0 ; Port B Open Drain Assignment 103 0 [$216C4] | PBDAT EQU REGB+$06C4 ; Port B Data Content 104 0 | * 105 0 [$21560] | PCDIR EQU REGB+$0560 ; Port C Data Direction Assignment 106 0 [$21562] | PCPAR EQU REGB+$0562 ; Port C Pin Assignment 107 0 [$21564] | PCSO EQU REGB+$0564 ; Port C Special Options 108 0 [$21566] | PCDAT EQU REGB+$0566 ; Port C Data Content 109 0 [$21568] | PCINT EQU REGB+$0568 ; Port C Interrupt Control 110 0 | *** Timer 1, 2, 3, 4 as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 3 Source file: ethn_ex1.asm 111 0 [$21580] | TGCR EQU REGB+$0580 ; Timer Global Configuration 112 0 | * 113 0 [$21590] | TMR1 EQU REGB+$0590 ; Timer1 Mode 114 0 [$21592] | TMR2 EQU REGB+$0592 ; Timer2 Mode 115 0 [$21594] | TRR1 EQU REGB+$0594 ; Timer1 Reference 116 0 [$21596] | TRR2 EQU REGB+$0596 ; Timer2 Reference 117 0 [$21598] | TCR1 EQU REGB+$0598 ; Timer1 Capture 118 0 [$2159A] | TCR2 EQU REGB+$059A ; Timer2 Capture 119 0 [$2159C] | TCN1 EQU REGB+$059C ; Timer1 Counter 120 0 [$2159E] | TCN2 EQU REGB+$059E ; Timer2 Counter 121 0 | * 122 0 [$215A0] | TMR3 EQU REGB+$05A0 ; Timer3 Mode 123 0 [$215A2] | TMR4 EQU REGB+$05A2 ; Timer4 Mode 124 0 [$215A4] | TRR3 EQU REGB+$05A4 ; Timer3 Reference 125 0 [$215A6] | TRR4 EQU REGB+$05A6 ; Timer4 Reference 126 0 [$215A8] | TCR3 EQU REGB+$05A8 ; Timer3 Capture 127 0 [$215AA] | TCR4 EQU REGB+$05AA ; Timer4 Capture 128 0 [$215AC] | TCN3 EQU REGB+$05AC ; Timer3 Counter 129 0 [$215AE] | TCN4 EQU REGB+$05AE ; Timer4 Counter 130 0 | * 131 0 [$215B0] | TER1 EQU REGB+$05B0 ; Timer1 Event 132 0 [$215B2] | TER2 EQU REGB+$05B2 ; Timer2 Event 133 0 [$215B4] | TER3 EQU REGB+$05B4 ; Timer3 Event 134 0 [$215B6] | TER4 EQU REGB+$05B6 ; Timer4 Event 135 0 | *** CP 136 0 [$215C0] | CR EQU REGB+$05C0 ; CP Command 137 0 [$215C4] | RCCR EQU REGB+$05C4 ; RISC Configuration 138 0 [$215D6] | RTER EQU REGB+$05D6 ; RISC Timer Event Register 139 0 [$215DA] | RTMR EQU REGB+$05DA ; RISC Timer Mask Register 140 0 | * BRG 1, 2, 3, 4 141 0 [$215F0] | BRGC1 EQU REGB+$05F0 ; BRG1 Configuration 142 0 [$215F4] | BRGC2 EQU REGB+$05F4 ; BRG2 Configuration 143 0 [$215F8] | BRGC3 EQU REGB+$05F8 ; BRG3 Configuration 144 0 [$215FC] | BRGC4 EQU REGB+$05FC ; BRG4 Configuration 145 0 | *** SCC 1, 2, 3, 4 146 0 | * SCC1 147 0 [$21600] | GSMR_L1 EQU REGB+$0600 ; SCC1 General Mode 148 0 [$21604] | GSMR_H1 EQU REGB+$0604 ; SCC1 General Mode 149 0 [$21608] | PSMR1 EQU REGB+$0608 ; SCC1 Protocol Specific Mode 150 0 [$2160C] | TODR1 EQU REGB+$060C ; SCC1 Transmit On Demand 151 0 [$2160E] | DSR1 EQU REGB+$060E ; SCC1 Data Sync 152 0 [$21610] | SCCE1 EQU REGB+$0610 ; SCC1 Event 153 0 [$21614] | SCCM1 EQU REGB+$0614 ; SCC1 Mask 154 0 [$21617] | SCCS1 EQU REGB+$0617 ; SCC1 Status 155 0 | 156 0 | 157 0 | * SCC2 158 0 [$21620] | GSMR_L2 EQU REGB+$0620 ; SCC2 General Mode 159 0 [$21624] | GSMR_H2 EQU REGB+$0624 ; SCC2 General Mode 160 0 [$21628] | PSMR2 EQU REGB+$0628 ; SCC2 Protocol Specific Mode 161 0 [$2162C] | TODR2 EQU REGB+$062C ; SCC2 Transmit On Demand 162 0 [$2162E] | DSR2 EQU REGB+$062E ; SCC2 Data Sync 163 0 [$21630] | SCCE2 EQU REGB+$0630 ; SCC2 Event 164 0 [$21634] | SCCM2 EQU REGB+$0634 ; SCC2 Mask 165 0 [$21637] | SCCS2 EQU REGB+$0637 ; SCC2 Status as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 4 Source file: ethn_ex1.asm 166 0 | * SCC3 167 0 [$21640] | GSMR_L3 EQU REGB+$0640 ; SCC3 General Mode 168 0 [$21644] | GSMR_H3 EQU REGB+$0644 ; SCC3 General Mode 169 0 [$21648] | PSMR3 EQU REGB+$0648 ; SCC3 Protocol Specific Mode 170 0 [$2164C] | TODR3 EQU REGB+$064C ; SCC3 Transmit On Demand 171 0 [$2164E] | DSR3 EQU REGB+$064E ; SCC3 Data Sync 172 0 [$21650] | SCCE3 EQU REGB+$0650 ; SCC3 Event 173 0 [$21654] | SCCM3 EQU REGB+$0654 ; SCC3 Mask 174 0 [$21657] | SCCS3 EQU REGB+$0657 ; SCC3 Status 175 0 | * SCC4 176 0 [$21660] | GSMR_L4 EQU REGB+$0660 ; SCC4 General Mode 177 0 [$21664] | GSMR_H4 EQU REGB+$0664 ; SCC4 General Mode 178 0 [$21668] | PSMR4 EQU REGB+$0668 ; SCC4 Protocol Specific Mode 179 0 [$2166C] | TODR4 EQU REGB+$066C ; SCC4 Transmit On Demand 180 0 [$2166E] | DSR4 EQU REGB+$066E ; SCC4 Data Sync 181 0 [$21670] | SCCE4 EQU REGB+$0670 ; SCC4 Event 182 0 [$21674] | SCCM4 EQU REGB+$0674 ; SCC4 Mask 183 0 [$21677] | SCCS4 EQU REGB+$0677 ; SCC4 Status 184 0 | *** SMC 1, 2 185 0 [$21682] | SMCMR1 EQU REGB+$0682 ; SMC1 Mode 186 0 [$21686] | SMCE1 EQU REGB+$0686 ; SMC1 Event 187 0 [$2168A] | SMCM1 EQU REGB+$068A ; SMC1 Mask 188 0 | * 189 0 [$21692] | SMCMR2 EQU REGB+$0692 ; SMC2 Mode 190 0 [$21696] | SMCE2 EQU REGB+$0696 ; SMC2 Event 191 0 [$2169A] | SMCM2 EQU REGB+$069A ; SMC2 Mask 192 0 | *** SPI 193 0 [$216A0] | SPMODE EQU REGB+$06A0 ; SPI Mode 194 0 [$216A6] | SPIE EQU REGB+$06A6 ; SPI Event 195 0 [$216AA] | SPIM EQU REGB+$06AA ; SPI Mask 196 0 [$216AD] | SPCOM EQU REGB+$06AD ; SPI Command 197 0 | *** PIP 198 0 [$216B2] | PIPC EQU REGB+$06B2 ; PIP Configuration 199 0 [$216B6] | PTRR EQU REGB+$06B6 ; PIP Timing Parameter 200 0 | *** Serial Interface 201 0 [$216E0] | SIMODE EQU REGB+$06E0 ; SI Mode 202 0 [$216E4] | SIGMR EQU REGB+$06E4 ; SI Global Mode 203 0 [$216E6] | SISTR EQU REGB+$06E6 ; SI Status 204 0 [$216E7] | SICMR EQU REGB+$06E7 ; SI Command 205 0 [$216EC] | SICR EQU REGB+$06EC ; SI Clock Routing 206 0 [$216F0] | SIRP EQU REGB+$06F0 ; SI RAM Pointer 207 0 [$21700] | SIRAM EQU REGB+$0700 ; SI Routing RAM 208 0 | 209 0 | ************************ END of SIM/CPM Register MAP 210 0 | 211 0 | ************************ SCC Parameters 212 0 | 213 0 | ****** SCC1 214 0 [$20C00] | RBASE1 EQU SCC1PB+$000 ; SCC1 RX BD Base Address 215 0 [$20C02] | TBASE1 EQU SCC1PB+$002 ; SCC1 TX BD Base Address 216 0 [$20C04] | RFCR1 EQU SCC1PB+$004 ; SCC1 RX Function Code 217 0 [$20C05] | TFCR1 EQU SCC1PB+$005 ; SCC1 TX Function Code 218 0 [$20C06] | MRBLR1 EQU SCC1PB+$006 ; SCC1 MAX Buffer Length - RX 219 0 [$20C08] | RSTATE1 EQU SCC1PB+$008 ; SCC1 RX Internal State 220 0 [$20C10] | RBPRT1 EQU SCC1PB+$010 ; SCC1 RX BD Pointer as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 5 Source file: ethn_ex1.asm 221 0 [$20C18] | TSTATE1 EQU SCC1PB+$018 ; SCC1 TX Internal State 222 0 [$20C20] | TBPRT1 EQU SCC1PB+$020 ; SCC1 TX BD Pointer 223 0 [$20C28] | RCRC1 EQU SCC1PB+$028 ; SCC1 Temp Receive CRC 224 0 [$20C2C] | TCRC1 EQU SCC1PB+$02C ; SCC1 Temp Transmit CRC 225 0 | ****** SCC2 226 0 [$20D00] | RBASE2 EQU SCC2PB+$000 ; SCC2 RX BD Base Address 227 0 [$20D02] | TBASE2 EQU SCC2PB+$002 ; SCC2 TX BD Base Address 228 0 [$20D04] | RFCR2 EQU SCC2PB+$004 ; SCC2 RX Function Code 229 0 [$20D05] | TFCR2 EQU SCC2PB+$005 ; SCC2 TX Function Code 230 0 [$20D06] | MRBLR2 EQU SCC2PB+$006 ; SCC2 MAX Buffer Length - RX 231 0 [$20D08] | RSTATE2 EQU SCC2PB+$008 ; SCC2 RX Internal State 232 0 [$20D10] | RBPRT2 EQU SCC2PB+$010 ; SCC2 RX BD Pointer 233 0 [$20D18] | TSTATE2 EQU SCC2PB+$018 ; SCC2 TX Internal State 234 0 [$20D20] | TBPRT2 EQU SCC2PB+$020 ; SCC2 TX BD Pointer 235 0 [$20D28] | RCRC2 EQU SCC2PB+$028 ; SCC2 Temp Receive CRC 236 0 [$20D2C] | TCRC2 EQU SCC2PB+$02C ; SCC2 Temp Transmit CRC 237 0 | ****** SCC3 238 0 [$20E00] | RBASE3 EQU SCC3PB+$000 ; SCC3 RX BD Base Address 239 0 [$20E02] | TBASE3 EQU SCC3PB+$002 ; SCC3 TX BD Base Address 240 0 [$20E04] | RFCR3 EQU SCC3PB+$004 ; SCC3 RX Function Code 241 0 [$20E05] | TFCR3 EQU SCC3PB+$005 ; SCC3 TX Function Code 242 0 [$20E06] | MRBLR3 EQU SCC3PB+$006 ; SCC3 MAX Buffer Length - RX 243 0 [$20E08] | RSTATE3 EQU SCC3PB+$008 ; SCC3 RX Internal State 244 0 [$20E10] | RBPRT3 EQU SCC3PB+$010 ; SCC3 RX BD Pointer 245 0 [$20E18] | TSTATE3 EQU SCC3PB+$018 ; SCC3 TX Internal State 246 0 [$20E20] | TBPRT3 EQU SCC3PB+$020 ; SCC3 TX BD Pointer 247 0 [$20E28] | RCRC3 EQU SCC3PB+$028 ; SCC3 Temp Receive CRC 248 0 [$20E2C] | TCRC3 EQU SCC3PB+$02C ; SCC3 Temp Transmit CRC 249 0 | ****** SCC4 250 0 [$20F00] | RBASE4 EQU SCC4PB+$000 ; SCC4 RX BD Base Address 251 0 [$20F02] | TBASE4 EQU SCC4PB+$002 ; SCC4 TX BD Base Address 252 0 [$20F04] | RFCR4 EQU SCC4PB+$004 ; SCC4 RX Function Code 253 0 [$20F05] | TFCR4 EQU SCC4PB+$005 ; SCC4 TX Function Code 254 0 [$20F06] | MRBLR4 EQU SCC4PB+$006 ; SCC4 MAX Buffer Length - RX 255 0 [$20F08] | RSTATE4 EQU SCC4PB+$008 ; SCC4 RX Internal State 256 0 [$20F10] | RBPRT4 EQU SCC4PB+$010 ; SCC4 RX BD Pointer 257 0 [$20F18] | TSTATE4 EQU SCC4PB+$018 ; SCC4 TX Internal State 258 0 [$20F20] | TBPRT4 EQU SCC4PB+$020 ; SCC4 TX BD Pointer 259 0 [$20F28] | RCRC4 EQU SCC4PB+$028 ; SCC4 Temp Receive CRC 260 0 [$20F2C] | TCRC4 EQU SCC4PB+$02C ; SCC4 Temp Transmit CRC 261 0 [$20F30] | CRC_C4 EQU SCC4PB+$030 ; SCC4 CRC Constant Total-Transparent 262 0 [$20F34] | CRC_P4 EQU SCC4PB+$034 ; SCC4 CRC Preset Total-Transparent 263 0 | 264 0 | ****** SMC1 => SMCA, simplify assembly coding 265 0 [$20E80] | RBASEA EQU SMC1PB+$000 ; SMC1 RX BD Base Address 266 0 [$20E82] | TBASEA EQU SMC1PB+$002 ; SMC1 TX BD Base Address 267 0 [$20E84] | RFCRA EQU SMC1PB+$004 ; SMC1 RX Function Code 268 0 [$20E85] | TFCRA EQU SMC1PB+$005 ; SMC1 TX Function Code 269 0 [$20E86] | MRBLRA EQU SMC1PB+$006 ; SMC1 MAX Buffer Length - RX 270 0 [$20E88] | RSTATEA EQU SMC1PB+$008 ; SMC1 RX Internal State 271 0 [$20E90] | RBPRTA EQU SMC1PB+$010 ; SMC1 RX BD Pointer 272 0 [$20E98] | TSTATEA EQU SMC1PB+$018 ; SMC1 TX Internal State 273 0 [$20EA0] | TBPRTA EQU SMC1PB+$020 ; SMC1 TX BD Pointer 274 0 | ****** SMC1 => SMCB 275 0 [$20F80] | RBASEB EQU SMC2PB+$000 ; SMC2 RX BD Base Address as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 6 Source file: ethn_ex1.asm 276 0 [$20F82] | TBASEB EQU SMC2PB+$002 ; SMC2 TX BD Base Address 277 0 [$20F84] | RFCRB EQU SMC2PB+$004 ; SMC2 RX Function Code 278 0 [$20F85] | TFCRB EQU SMC2PB+$005 ; SMC2 TX Function Code 279 0 [$20F86] | MRBLRB EQU SMC2PB+$006 ; SMC2 MAX Buffer Length - RX 280 0 [$20F88] | RSTATEB EQU SMC2PB+$008 ; SMC2 RX Internal State 281 0 [$20F90] | RBPRTB EQU SMC2PB+$010 ; SMC2 RX BD Pointer 282 0 [$20F98] | TSTATEB EQU SMC2PB+$018 ; SMC2 TX Internal State 283 0 [$20FA0] | TBPRTB EQU SMC2PB+$020 ; SMC2 TX BD Pointer 284 0 | 285 0 | 286 0 | 287 0 | ************************** Specific Parameters 288 0 | 289 0 | * SCC1, Ethernet Specific Parameter 290 0 [$20C34] | C_PRES1 EQU SCC1PB+$34 ; SCC1 Preset CRC ($FFFFFFFF) 291 0 [$20C30] | C_MASK1 EQU SCC1PB+$30 ; SCC1 Constant mask for CRC($20E3DEBB) 292 0 [$20C38] | CRCEC1 EQU SCC1PB+$38 ; SCC1 CRC error counter 293 0 [$20C3C] | ALEC1 EQU SCC1PB+$3C ; SCC1 alignment error counter 294 0 [$20C40] | DISFC1 EQU SCC1PB+$40 ; SCC1 discard frame counter 295 0 [$20C44] | PADS1 EQU SCC1PB+$44 ; SCC1 short frame PAD counter 296 0 [$20C46] | RET_Lim1 EQU SCC1PB+$46 ; SCC1 retry limit threshold 297 0 [$20C48] | RET_cnt1 EQU SCC1PB+$48 ; SCC1 retry limit counter 298 0 [$20C4A] | MFLR1 EQU SCC1PB+$4A ; SCC1 max. frame length reg. 299 0 [$20C4C] | MINFLR1 EQU SCC1PB+$4C ; SCC1 min. frame length reg. 300 0 [$20C4E] | MAXD11 EQU SCC1PB+$4E ; SCC1 max. DMA1 length reg. 301 0 [$20C50] | MAXD21 EQU SCC1PB+$50 ; SCC1 max. DMA2 length reg. 302 0 [$20C52] | MAXD1 EQU SCC1PB+$52 ; SCC1 Rx max DMA 303 0 [$20C54] | DMA_cnt1 EQU SCC1PB+$54 ; SCC1 Rx DMA count 304 0 [$20C56] | MAX_b1 EQU SCC1PB+$56 ; SCC1 max BD byte count 305 0 [$20C58] | GADDR11 EQU SCC1PB+$58 ; SCC1 Group Addr. Filter 1 306 0 [$20C5A] | GADDR21 EQU SCC1PB+$5A ; SCC1 Group Addr. Filter 2 307 0 [$20C5C] | GADDR31 EQU SCC1PB+$5C ; SCC1 Group Addr. Filter 3 308 0 [$20C5E] | GADDR41 EQU SCC1PB+$5E ; SCC1 Group Addr. Filter 4 309 0 [$20C60] | TBUF0.data01 EQU SCC1PB+$60 ; SCC1 save area 0 - current frame 310 0 [$20C64] | TBUF0.data11 EQU SCC1PB+$64 ; SCC1 save area 1 - current frame 311 0 [$20C68] | TBUF0.rba01 EQU SCC1PB+$68 ; SCC1 312 0 [$20C6C] | TBUF0.crc1 EQU SCC1PB+$6C ; SCC1 313 0 [$20C70] | TBUF0.bcnt1 EQU SCC1PB+$70 ; SCC1 314 0 [$20C72] | PADDR1_H1 EQU SCC1PB+$72 ; physical address 1 (MSB) 315 0 [$20C74] | PADDR1_M1 EQU SCC1PB+$74 ; physical address 1 316 0 [$20C76] | PADDR1_L1 EQU SCC1PB+$76 ; physical address 1 (LSB) 317 0 [$20C78] | P_PER1 EQU SCC1PB+$78 ; persistence 318 0 [$20C7A] | RFBD_ptr1 EQU SCC1PB+$7A ; Rx first BD pointer 319 0 [$20C7C] | TFBD_ptr1 EQU SCC1PB+$7C ; Tx first BD pointer 320 0 [$20C7E] | TLBD_ptr1 EQU SCC1PB+$7E ; Tx last BD pointer 321 0 [$20C80] | TBUF1.data01 EQU SCC1PB+$80 ; SCC1 save area 0 - next frame 322 0 [$20C84] | TBUF1.data11 EQU SCC1PB+$84 ; SCC1 save area 1 - next frame 323 0 [$20C88] | TBUF1.rba01 EQU SCC1PB+$88 ; SCC1 324 0 [$20C8C] | TBUF1.crc1 EQU SCC1PB+$8C ; SCC1 325 0 [$20C90] | TBUF1.bcnt1 EQU SCC1PB+$90 ; SCC1 326 0 [$20C92] | TX_len1 EQU SCC1PB+$92 ; SCC1 Tx frame length counter 327 0 [$20C94] | IADDR11 EQU SCC1PB+$94 ; SCC1 Individual Addr. Filter 1 328 0 [$20C96] | IADDR21 EQU SCC1PB+$96 ; SCC1 Individual Addr. Filter 2 329 0 [$20C98] | IADDR31 EQU SCC1PB+$98 ; SCC1 Individual Addr. Filter 3 330 0 [$20C9A] | IADDR41 EQU SCC1PB+$9A ; SCC1 Individual Addr. Filter 4 as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 7 Source file: ethn_ex1.asm 331 0 [$20C9C] | BOFF_CNT1 EQU SCC1PB+$9C ; back off counter 332 0 [$20C9E] | TADDR1_H1 EQU SCC1PB+$9E ; temp address (MSB) 333 0 [$20CA0] | TADDR1_M1 EQU SCC1PB+$A0 ; temp address 334 0 [$20CA2] | TADDR1_L1 EQU SCC1PB+$A2 ; temp address (LSB) 335 0 | 336 0 | * SCC2, HDLC Specific Parameters 337 0 [$20D34] | C_MASK2 EQU SCC2PB+$34 ; SCC2 CRC Constant 338 0 [$20D38] | C_PRES2 EQU SCC2PB+$38 ; SCC2 CRC Preset 339 0 [$20D3C] | DISFC2 EQU SCC2PB+$3C ; SCC2 Discard Frame Counter 340 0 [$20D3E] | CRCEC2 EQU SCC2PB+$3E ; SCC2 CRC Error Counter 341 0 [$20D40] | ABTSC2 EQU SCC2PB+$40 ; SCC2 Abort Sequence Counter 342 0 [$20D42] | NMARC2 EQU SCC2PB+$42 ; SCC2 NonMatch Addr Rx Counter 343 0 [$20D44] | RETRC2 EQU SCC2PB+$44 ; SCC2 Frame ReTRansmit Counter 344 0 [$20D46] | MFLR2 EQU SCC2PB+$46 ; SCC2 Max Frame Length Register 345 0 [$20D48] | MAXCNT2 EQU SCC2PB+$48 ; SCC2 MAX length Counter 346 0 [$20D4A] | RFTHR2 EQU SCC2PB+$4A ; SCC2 Receive Frames THreshold 347 0 [$20D4C] | RFCNT2 EQU SCC2PB+$4C ; SCC2 Receive Frames Count 348 0 [$20D4E] | HMASK2 EQU SCC2PB+$4E ; SCC2 Frame Address Mask (U-D) 349 0 [$20D50] | HADDR12 EQU SCC2PB+$50 ; SCC2 Frame Address 1 350 0 [$20D52] | HADDR22 EQU SCC2PB+$52 ; SCC2 Frame Address 2 351 0 [$20D54] | HADDR32 EQU SCC2PB+$54 ; SCC2 Frame Address 3 352 0 [$20D56] | HADDR42 EQU SCC2PB+$56 ; SCC2 Frame Address 4 353 0 | 354 0 | * SCC4, HDLC Specific Parameters 355 0 [$20F34] | C_MASK4 EQU SCC4PB+$34 ; SCC4 CRC Constant 356 0 [$20F38] | C_PRES4 EQU SCC4PB+$38 ; SCC4 CRC Preset 357 0 [$20F3C] | DISFC4 EQU SCC4PB+$3C ; SCC4 Discard Frame Counter 358 0 [$20F3E] | CRCEC4 EQU SCC4PB+$3E ; SCC4 CRC Error Counter 359 0 [$20F40] | ABTSC4 EQU SCC4PB+$40 ; SCC4 Abort Sequence Counter 360 0 [$20F42] | NMARC4 EQU SCC4PB+$42 ; SCC4 NonMatch Addr Rx Counter 361 0 [$20F44] | RETRC4 EQU SCC4PB+$44 ; SCC4 Frame ReTRansmit Counter 362 0 [$20F46] | MFLR4 EQU SCC4PB+$46 ; SCC4 Max Frame Length Register 363 0 [$20F48] | MAXCNT4 EQU SCC4PB+$48 ; SCC4 MAX length Counter 364 0 [$20F4A] | RFTHR4 EQU SCC4PB+$4A ; SCC4 Receive Frames THreshold 365 0 [$20F4C] | RFCNT4 EQU SCC4PB+$4C ; SCC4 Receive Frames Count 366 0 [$20F4E] | HMASK4 EQU SCC4PB+$4E ; SCC4 Frame Address Mask (U-D) 367 0 [$20F50] | HADDR14 EQU SCC4PB+$50 ; SCC4 Frame Address 1 368 0 [$20F52] | HADDR24 EQU SCC4PB+$52 ; SCC4 Frame Address 2 369 0 [$20F54] | HADDR34 EQU SCC4PB+$54 ; SCC4 Frame Address 3 370 0 [$20F56] | HADDR44 EQU SCC4PB+$56 ; SCC4 Frame Address 4 371 0 | 372 0 | 373 0 | * SCC4, UART Specific Parameters 374 0 [$20F38] | MAXIDL4 EQU SCC4PB+$38 ; SCC4 MAX IDLe cchars 375 0 [$20F3A] | IDLC4 EQU SCC4PB+$3A ; SCC4 temp IDLe Counter 376 0 [$20F3C] | BRKCR4 EQU SCC4PB+$3C ; SCC4 BReaK Count Register (TX) 377 0 [$20F3E] | PAREC4 EQU SCC4PB+$3E ; SCC4 Parity Error Counter (RX) 378 0 [$20F40] | FRMER4 EQU SCC4PB+$40 ; SCC4 Framing Error Counter (RX) 379 0 [$20F42] | NOSEC4 EQU SCC4PB+$42 ; SCC4 Noise Counter (RX) 380 0 [$20F44] | BRKEC4 EQU SCC4PB+$44 ; SCC4 BReaK Condition Counter (RX) 381 0 [$20F46] | BRKLN4 EQU SCC4PB+$46 ; SCC4 Last BReaK Length (RX) 382 0 [$20F48] | UADDR14 EQU SCC4PB+$48 ; SCC4 UART Address Character 1 383 0 [$20F4A] | UADDR24 EQU SCC4PB+$4A ; SCC4 UART Address Character 2 384 0 [$20F4C] | RETMP4 EQU SCC4PB+$4C ; SCC4 Temp storage 385 0 [$20F4E] | TOSEQ4 EQU SCC4PB+$4E ; SCC4 TX out of sequence Character as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 8 Source file: ethn_ex1.asm 386 0 [$20F50] | CCHAR14 EQU SCC4PB+$50 ; SCC4 Control Character 1 387 0 [$20F52] | CCHAR24 EQU SCC4PB+$52 ; SCC4 Control Character 2 388 0 [$20F54] | CCHAR34 EQU SCC4PB+$54 ; SCC4 Control Character 3 389 0 [$20F56] | CCHAR44 EQU SCC4PB+$56 ; SCC4 Control Character 4 390 0 [$20F58] | CCHAR54 EQU SCC4PB+$58 ; SCC4 Control Character 5 391 0 [$20F5A] | CCHAR64 EQU SCC4PB+$5A ; SCC4 Control Character 6 392 0 [$20F5C] | CCHAR74 EQU SCC4PB+$5C ; SCC4 Control Character 7 393 0 [$20F5E] | CCHAR84 EQU SCC4PB+$5E ; SCC4 Control Character 8 394 0 [$20F60] | RCCM4 EQU SCC4PB+$60 ; SCC4 RX Control Character Mask 395 0 [$20F62] | RCCR4 EQU SCC4PB+$62 ; SCC4 RX Control Character 396 0 [$20F64] | RLBC4 EQU SCC4PB+$64 ; SCC4 RX Last Break Character 397 0 | 398 0 | * SCC3, BISYNC Specific Parameters 399 0 [$20E38] | CRCC3 EQU SCC3PB+$38 ; SCC3 CRC Constant Temp Value 400 0 [$20E3A] | PRCRC3 EQU SCC3PB+$3A ; SCC3 Preset RX CRC16/LRC 401 0 [$20E3C] | PTCRC3 EQU SCC3PB+$3C ; SCC3 Preset TX CRC16/LRC 402 0 [$20E3E] | PAREC3 EQU SCC3PB+$3E ; SCC3 Parity Error Counter (RX) 403 0 [$20E40] | BSYNC3 EQU SCC3PB+$40 ; SCC3 BISYNC SYNC Character 404 0 [$20E42] | BIDLE3 EQU SCC3PB+$42 ; SCC3 BISYNC IDLE Character 405 0 [$20E44] | CCHAR13 EQU SCC3PB+$44 ; SCC3 Control Character 1 406 0 [$20E46] | CCHAR23 EQU SCC3PB+$46 ; SCC3 Control Character 2 407 0 [$20E48] | CCHAR33 EQU SCC3PB+$48 ; SCC3 Control Character 3 408 0 [$20E4A] | CCHAR43 EQU SCC3PB+$4A ; SCC3 Control Character 4 409 0 [$20E4C] | CCHAR53 EQU SCC3PB+$4C ; SCC3 Control Character 5 410 0 [$20E4E] | CCHAR63 EQU SCC3PB+$4E ; SCC3 Control Character 6 411 0 [$20E50] | CCHAR73 EQU SCC3PB+$50 ; SCC3 Control Character 7 412 0 [$20E52] | CCHAR83 EQU SCC3PB+$52 ; SCC3 Control Character 8 413 0 [$20E54] | RCCM3 EQU SCC3PB+$54 ; SCC3 RX Control Character Mask 414 0 | 415 0 | * SMC1, UART Specific Parameters 416 0 [$20EA8] | MAXIDLA EQU SMC1PB+$28 ; SMC1 MAX IDLe cchars 417 0 [$20EAA] | IDLCA EQU SMC1PB+$2A ; SMC1 temp IDLe Counter 418 0 [$20EAC] | BRKLA EQU SMC1PB+$2C ; SMC1 last Received BReaK char length 419 0 [$20EAE] | BRKECA EQU SMC1PB+$2E ; SMC1 receive BReaK Condition Counter 420 0 [$20EB0] | BRKCRA EQU SMC1PB+$30 ; SMC1 BReaK Count Register (TX) 421 0 | 422 0 | 423 0 | 424 0 > | ORG INIT 425 402000 | 426 402000 | 427 402000 33FC030300021552 | MOVE.W #$0303,PAPAR ; port A pin 1+2+8+9 - dedicated function (RXD,TXD,CLK1+2) 428 402008 33FC000000021550 | MOVE.W #$0000,PADIR ; all port A pins inputs 429 402010 | 430 402010 33FC000000021562 | MOVE.W #$0000,PCPAR ; port C select RTS1(TENA),CTS1(CLSN),CD1(RENA) 431 402018 | * ; but do not enable TENA jet $0001 432 402018 427900021560 | CLR.W PCDIR 433 40201E 33FC003000021564 | MOVE.W #$0030,PCSO ; port C CTS1(CLSN) and CD1 (RENA) 434 402026 | 435 402026 33FC07500002151E | MOVE.W #$0750,SDCR ; Interrupt service mask = 7 and arbit. ID = 5 436 40202E | 437 40202E | * this example is running in normal mode, but you can also use it in loopback 438 40202E | * for loopback mode take the '*' lines and comment out the related once. 439 40202E | 440 40202E | as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 9 Source file: ethn_ex1.asm 441 40202E 23FC00000024000216 | MOVE.L #$00000024,SICR ; route CLK1+2 to SCC1 and select NMSI pins EC | 442 402038 | 443 402038 | 444 402038 | * MOVE.L #$00010002,BRGC2 ; if you want to use loopback mode, you have 445 402038 | * MOVE.L #$00000009,SICR ; generate an ext. clock. BRGC2 is generating 446 402038 | * ; a clock and this clk is routed to RCLK and 447 402038 | * ; TCLK of SCC1. 448 402038 | 449 402038 33FC000000020C00 | MOVE.W #$0000,RBASE1 ; receive buffer dis. 450 402040 33FC000800020C02 | MOVE.W #$0008,TBASE1 ; trans. buffer dis. 451 402048 13FC001500020C04 | MOVE.B #$15,RFCR1 ; normal mode for receive 452 402050 13FC001500020C05 | MOVE.B #$15,TFCR1 ; normal mode for trans. 453 402058 33FC05F000020F06 | MOVE.W #$05F0,MRBLR4 ; max. bytes per receiver (1520) 454 402060 | 455 402060 33FC0001000215C0 | MOVE.W #$0001,CR ; initalize transmit and receive parameter of SCC1 456 402068 | 457 402068 23FCDEBB20E300020C | MOVE.L #$DEBB20E3,C_MASK1 ; 32 Bit CCITT CRC 30 | 458 402072 23FCFFFFFFFF00020C | MOVE.L #$FFFFFFFF,C_PRES1 ; 32 Bit CCITT CRC 34 | 459 40207C 23FC0000000000020C | MOVE.L #$0,CRCEC1 38 | 460 402086 23FC0000000000020C | MOVE.L #$0,ALEC1 3C | 461 402090 23FC0000000000020C | MOVE.L #$0,DISFC1 40 | 462 40209A 33FC888800020C44 | MOVE.W #$8888,PADS1 463 4020A2 33FC000F00020C46 | MOVE.W #$000F,RET_Lim1 464 4020AA 33FC05EE00020C4A | MOVE.W #$05EE,MFLR1 465 4020B2 33FC004000020C4C | MOVE.W #$0040,MINFLR1 466 4020BA 33FC05EE00020C4E | MOVE.W #$05EE,MAXD11 467 4020C2 33FC05EE00020C50 | MOVE.W #$05EE,MAXD21 468 4020CA 33FC05EE00020C54 | MOVE.W #$05EE,DMA_cnt1 469 4020D2 33FC000000020C58 | MOVE.W #$0,GADDR11 470 4020DA 33FC000000020C5A | MOVE.W #$0,GADDR21 471 4020E2 33FC000000020C5C | MOVE.W #$0,GADDR31 472 4020EA 33FC000000020C5E | MOVE.W #$0,GADDR41 473 4020F2 33FC000000020C72 | MOVE.W #$0000,PADDR1_H1 474 4020FA 33FC000000020C74 | MOVE.W #$0000,PADDR1_M1 475 402102 33FC004000020C76 | MOVE.W #$0040,PADDR1_L1 476 40210A 33FC000000020C78 | MOVE.W #$0000,P_PER1 477 402112 33FC000000020C94 | MOVE.W #$0,IADDR11 478 40211A 33FC000000020C96 | MOVE.W #$0,IADDR21 479 402122 33FC000000020C98 | MOVE.W #$0,IADDR31 480 40212A 33FC000000020C9A | MOVE.W #$0,IADDR41 481 402132 33FC000000020C9E | MOVE.W #$0,TADDR1_H1 482 40213A 33FC000000020CA0 | MOVE.W #$0,TADDR1_M1 483 402142 33FC000000020CA2 | MOVE.W #$0,TADDR1_L1 484 40214A | 485 40214A | 486 40214A 33FCB00000020000 | MOVE.W #$B000,RXBD+$0000 ; RxBD status reg. 487 402152 33FC000000020002 | MOVE.W #$0000,RXBD+$0002 ; data length reg. 488 40215A 23FC00404000000200 | MOVE.L #$00404000,RXBD+$0004 ; pointer to data at $404000 04 | as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc. May 5 1993 09:39:47 10 Source file: ethn_ex1.asm 489 402164 | 490 402164 33FCFC0000020008 | MOVE.W #$FC00,TXBD+$0000 ; TxBD status reg. 491 40216C 33FC000D0002000A | MOVE.W #$000D,TXBD+$0002 ; data length reg. 492 402174 23FC00404100000200 | MOVE.L #$00404100,TXBD+$0004 ; pointer to data at $404100 0C | 493 40217E | 494 40217E 33FCFFFF00021610 | MOVE.W #$FFFF,SCCE1 ; clears all pending events of SCC1 495 402186 33FC001A00021614 | MOVE.W #$001A,SCCM1 ; enable TXE, RXF and TXB interrupts 496 40218E | 497 40218E | * the next two lines would let the SCC1 generate an interrupt to the system. 498 40218E | * don't forget to clear the interrupt pending register, if you use this option. 499 40218E | 500 40218E | * MOVE.L #$00E44000,CICR ; interrupt configuraton reg. 501 40218E | * MOVE.L #$40000000,CIMR ; allow SCC1 a system interrupt 502 40218E | 503 40218E 23FC00000000000216 | MOVE.L #$00000000,GSMR_H1 04 | 504 402198 | 505 402198 | * MOVE.L #$1088004C,GSMR_L1 ; SCC1 conf. reg. set to automatic 506 402198 | * ; control of CLSN and RENA, more setup 507 402198 | * ; time for the EEST, loopback and ethernet mode. 508 402198 | * ; ENR and ENT are not enabled jet. 509 402198 | 510 402198 23FC1088000C000216 | MOVE.L #$1088000C,GSMR_L1 ; SCC1 conf. reg. set to automatic 00 | 511 4021A2 | * ; control of CLSN and RENA, more setup 512 4021A2 | * ; time for the EEST and ethernet mode. 513 4021A2 | * ; ENR and ENT are not enabled jet. 514 4021A2 | 515 4021A2 | * MOVE.W #$2A4A,PSMR1 ; ethernet mode reg. is set to receive 516 4021A2 | * ; short frames, 32 bit CRC, reject all frames, 517 4021A2 | * ; loop operation and begin searching for the 518 4021A2 | * ; start frame delimiter 22 bits after RENA 519 4021A2 | 520 4021A2 33FC2A4A00021608 | MOVE.W #$2A4A,PSMR1 ; ethernet mode reg. is set to receive 521 4021AA | * ; short frames, 32 bit CRC, reject all frames, 522 4021AA | * ; and begin searching for the 523 4021AA | * ; start frame delimiter 22 bits after RENA MOVE.W #$D555,DSR1 524 4021AA | 525 4021AA 33FCD5550002160E | MOVE.W #$D555,DSR1 526 4021B2 | 527 4021B2 33FC000100021562 | MOVE.W #$0001,PCPAR ; enable TENA 528 4021BA | 529 4021BA | * MOVE.L #$1088007C,GSMR_L1 ; enable transmitter in loopback mode 530 4021BA | 531 4021BA 23FC1088003C000216 | MOVE.L #$1088003C,GSMR_L1 ; enable transmitter in normal mode 00 | 532 4021C4 | 533 4021C4 | END