/*********************************************************************** 
* NOTICE
* All files contained on this disk are subject to the licensing conditions
* issued by MOTOROLA Inc.
*
* All files are copyright 1993 by MOTOROLA Inc. 
************************************************************************/


/********************************************************
 * File:	hdlc.c
 *
 * Description:
 *	The driver routines for handling an HDLC port.
 *
 * Routines:
 *	hdlc_init
 *	hdlc_status
 *
 * Author:
 *	Jonathan Masel
 ********************************************************/

#include "gct.h"
#include "config.h"
#include "types.h"
#include "mtypes.h"
#include "msg.h"
#include "bss.h"
#include "quicc.h"
#include "states.h"
#include "hdlc.h"





/********************************************************
 * routine:	hdlc_init
 *
 * description:
 *	Initialize the driver tables for
 *	HDLC ports.
 *
 * arguments:
 *	n		the driver's child number
 *			(i.e. which port)
 *	hdlc		points to an scc configuration structure
 *
 * return code:
 *
 * side effects:
 *
 ********************************************************/
hdlc_init(n, scc)
int n;
struct scc *scc;
{
	GCT *gct;
	int (* *protocol)();
	unsigned adr, rom;
	WORK_AREA *wa;
	extern int hdlc_txreq(), hdlc_rxfr(),
		hdlc_conf(), hdlc_txerr(),
		hdlc_busy(),
		return_to_pool(), hdlc_status(), hdlc_abort();

	GETGCT(gct);
	protocol = gct->driver->protocol;
	wa = (WORK_AREA *)gct->driver->child[n].work_area;
	rom = gct->driver->rom;

	adr = (unsigned)hdlc_txreq + rom;
	protocol[SUB(TX_REQ) | HDLC_STATE] = (int (*)())adr;
	adr = (unsigned)hdlc_rxfr + rom;
	protocol[SUB(RX_IND) | HDLC_STATE] = (int (*)())adr;
	adr = (unsigned)hdlc_conf + rom;
	protocol[SUB(TX_CONF) | HDLC_STATE] = (int (*)())adr;
	adr = (unsigned)hdlc_txerr + rom;
	protocol[SUB(TX_ERR) | HDLC_STATE] = (int (*)())adr;
	adr = (unsigned)hdlc_busy + rom;
	protocol[SUB(BUSY) | HDLC_STATE] = (int (*)())adr;
	adr = (unsigned)return_to_pool + rom;
	protocol[SUB(RTP) | HDLC_STATE] = (int (*)())adr;
	adr = (unsigned)hdlc_status + rom;
	protocol[SUB(STATUS) | HDLC_STATE] = (int (*)())adr;
	adr = (unsigned)hdlc_abort + rom;
	protocol[SUB(ABORT) | HDLC_STATE] = (int (*)())adr;

	gct->driver->child[n].upper = scc->upper;
	gct->driver->child[n].state = HDLC_STATE;
	gct->driver->child[n].smac = &protocol[HDLC_STATE];
	/*
	 * set constant HDLC status bits for
	 * first BD's in a frame and
	 * last BD's in a frame
	 */
	wa->BDlast = T_I | T_L | T_CRC;
	wa->BDfirst = 0;
	wa->BDrx = 0;
	wa->intr_rxfr = HDLC_RXF;
	wa->intr_txbd = HDLC_TBD;
	wa->intr_terr = HDLC_TXE;
	wa->intr_busy = HDLC_BSY;
	wa->fr_lng = scc->mrblr;
	wa->t_error = HDLC_T_ERROR;

	/*
	 * initialize hdlc parameter ram
	 */
	wa->pram->pscc.h.c_mask = scc->pram.h.c_mask;
	wa->pram->pscc.h.c_pres = scc->pram.h.c_pres;
	wa->pram->pscc.h.disfc = scc->pram.h.disfc;
	wa->pram->pscc.h.crcec = scc->pram.h.crcec;
	wa->pram->pscc.h.abtsc = scc->pram.h.abtsc;
	wa->pram->pscc.h.nmarc = scc->pram.h.nmarc;
	wa->pram->pscc.h.retrc = scc->pram.h.retrc;
	wa->pram->pscc.h.mflr = scc->pram.h.mflr;
	wa->pram->pscc.h.rfthr = scc->pram.h.rfthr;
	wa->pram->pscc.h.hmask = scc->pram.h.hmask;
	wa->pram->pscc.h.haddr1 = scc->pram.h.haddr1;
	wa->pram->pscc.h.haddr2 = scc->pram.h.haddr2;
	wa->pram->pscc.h.haddr3 = scc->pram.h.haddr3;
	wa->pram->pscc.h.haddr4 = scc->pram.h.haddr4;

}

hdlc_status()
{
}