as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc.     May  5 1993  09:43:09      1
Source file: uart_ex1.asm

1      0                            |  	*
2      0                            |  	*               Header File for the QUICC ( MC68360 )
3      0                            |  	*               UART Example User's Manual Page 7-170      PH 5/5/93
4      0                            |  	***********************************************************************
5      0                            |  	*
6      0        [$402000]           |  	INIT    EQU     $0402000        ; QUADS Board DRAM User Space
7      0                            |  	
8      0                            |  	************************** DUAL PORT RAM ******************************
9      0        [$3FF00]            |  	MBAR    EQU     $03FF00 ; Module Base Address, (MBAR)=REGB
10     0                            |  	*MBAR   EQU     $03FF04 ; Module Base Address,in SLAVE mode
11     0        [$3FF08]            |  	MBARE   EQU     $03FF08 ; Module Base Address Enable SLAVE
12     0                            |  	*
13     0        [$20000]            |  	DPRBASE EQU     $00020000       ; Base address of dual-port RAM
14     0        [$20000]            |  	RXBD    EQU     DPRBASE+$0000   ; Receive Buffer Discriptor address
15     0        [$20008]            |  	TXBD    EQU     DPRBASE+$0008   ; Transmit Buffer Discriptor address
16     0        [$21000]            |  	REGB    EQU     DPRBASE+$1000   ; Base address of Internal Registers
17     0        [$20C00]            |  	SCC1PB  EQU     DPRBASE+$0C00   ; SCC1 Protocol Base address
18     0        [$20D00]            |  	SCC2PB  EQU     DPRBASE+$0D00   ; SCC2 Protocol Base address
19     0        [$20E00]            |  	SCC3PB  EQU     DPRBASE+$0E00   ; SCC3 Protocol Base address
20     0        [$20F00]            |  	SCC4PB  EQU     DPRBASE+$0F00   ; SCC4 Protocol Base address
21     0        [$20D80]            |  	SPIPB   EQU     DPRBASE+$0D80   ; SPI Protocol Base
22     0        [$20E80]            |  	SMC1PB  EQU     DPRBASE+$0E80   ; SMC1 Protocol Base
23     0        [$20F80]            |  	SMC2PB  EQU     DPRBASE+$0F80   ; SMC2 Protocol Base
24     0        [$20E70]            |  	IDMA1PB EQU     DPRBASE+$0E70   ; IDMA1 Protocol Base
25     0        [$20F70]            |  	IDMA2PB EQU     DPRBASE+$0F70   ; IDMA2 Protocol Base
26     0                            |  	
27     0                            |  	************************ SIM Module registers **************************
28     0        [$21000]            |  	MCR     EQU     REGB+$0000      ; Module Configuration
29     0        [$21008]            |  	AVR     EQU     REGB+$0008      ; Auto Vector
30     0        [$21009]            |  	RSR     EQU     REGB+$0009      ; Reset Status
31     0        [$2100C]            |  	CLKOCR  EQU     REGB+$000C      ; CLKO Control
32     0        [$21010]            |  	PPLCR   EQU     REGB+$0010      ; PPL Control
33     0        [$21014]            |  	CDVCR   EQU     REGB+$0014      ; Clock Divider Control
34     0                            |  	*
35     0        [$21016]            |  	PEPAR   EQU     REGB+$0016      ; Port E Pin Assignment
36     0                            |  	*
37     0        [$21022]            |  	SYPCR   EQU     REGB+$0022      ; System Protection Control
38     0        [$21023]            |  	SWIV    EQU     REGB+$0023      ; S/w Interrupt Vector
39     0        [$21026]            |  	PICR    EQU     REGB+$0026      ; Periodic Interrupt Control
40     0        [$2102A]            |  	PITR    EQU     REGB+$002A      ; Periodic Interrupt Timing
41     0        [$2102F]            |  	SWSR    EQU     REGB+$002F      ; S/w Service
42     0        [$21032]            |  	BKAR    EQU     REGB+$0032      ; Breakpoint Address
43     0        [$21034]            |  	BKCQ    EQU     REGB+$0034      ; Breakpoint Control
44     0                            |  	*
45     0        [$21040]            |  	GMR     EQU     REGB+$0040      ; Global Memory
46     0        [$21044]            |  	MSTAT   EQU     REGB+$0044      ; MEMC Status
47     0                            |  	*
48     0        [$21050]            |  	BR0     EQU     REGB+$0050      ; Base Register 0
49     0        [$21054]            |  	OR0     EQU     REGB+$0054      ; Option Register 0
50     0        [$21060]            |  	BR1     EQU     REGB+$0060      ; Base Register 1
51     0        [$21064]            |  	OR1     EQU     REGB+$0064      ; Option Register 1
52     0        [$21070]            |  	BR2     EQU     REGB+$0070      ; Base Register 2
53     0        [$21074]            |  	OR2     EQU     REGB+$0074      ; Option Register 2
54     0        [$21080]            |  	BR3     EQU     REGB+$0080      ; Base Register 3
55     0        [$21084]            |  	OR3     EQU     REGB+$0084      ; Option Register 3
as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc.     May  5 1993  09:43:09      2
Source file: uart_ex1.asm

56     0        [$21090]            |  	BR4     EQU     REGB+$0090      ; Base Register 4
57     0        [$21094]            |  	OR4     EQU     REGB+$0094      ; Option Register 4
58     0        [$210A0]            |  	BR5     EQU     REGB+$00A0      ; Base Register 5
59     0        [$210A4]            |  	OR5     EQU     REGB+$00A4      ; Option Register 5
60     0        [$210B0]            |  	BR6     EQU     REGB+$00B0      ; Base Register 6
61     0        [$210B4]            |  	OR6     EQU     REGB+$00B4      ; Option Register 6
62     0        [$210C0]            |  	BR7     EQU     REGB+$00C0      ; Base Register 7
63     0        [$210C4]            |  	OR7     EQU     REGB+$00C4      ; Option Register 7
64     0                            |  	*
65     0                            |  	************************ CPM Module registers *******************
66     0                            |  	*
67     0        [$21500]            |  	ICCR    EQU     REGB+$0500      ; Channel Configuration
68     0                            |  	*** IDMA1, 2
69     0        [$21504]            |  	CMR1    EQU     REGB+$0504      ; IDMA1 Mode
70     0        [$21508]            |  	SAPR1   EQU     REGB+$0508      ; IDMA1 Source Address Pointer
71     0        [$2150C]            |  	DAPR1   EQU     REGB+$050C      ; IDMA1 destination Address Pointer
72     0        [$21510]            |  	BCR1    EQU     REGB+$0510      ; IDMA1 Byte Count
73     0        [$21514]            |  	FCR1    EQU     REGB+$0514      ; IDMA1 Fuction Code
74     0        [$21516]            |  	CMAR1   EQU     REGB+$0516      ; IDMA1 Channel Mask
75     0        [$21518]            |  	CSR1    EQU     REGB+$0518      ; IDMA1 Channel Status
76     0                            |  	*
77     0        [$21526]            |  	CMR2    EQU     REGB+$0526      ; IDMA2 Mode
78     0        [$21528]            |  	SAPR2   EQU     REGB+$0528      ; IDMA2 Source Address Pointer
79     0        [$2152C]            |  	DAPR2   EQU     REGB+$052C      ; IDMA2 destination Address Pointer
80     0        [$21530]            |  	BCR2    EQU     REGB+$0530      ; IDMA2 Byte Count
81     0        [$21534]            |  	FCR2    EQU     REGB+$0534      ; IDMA2 Fuction Code
82     0        [$21536]            |  	CMAR2   EQU     REGB+$0536      ; IDMA2 Channel Mask
83     0        [$21538]            |  	CSR2    EQU     REGB+$0538      ; IDMA2 Channel Status
84     0                            |  	*** SDMA
85     0        [$2151C]            |  	SDSR    EQU     REGB+$051C      ; SDMA Status
86     0        [$2151E]            |  	SDCR    EQU     REGB+$051E      ; SDMA Configuration Register
87     0        [$21520]            |  	SDAR    EQU     REGB+$0520      ; SDMA Address Register
88     0                            |  	*** CP Interrupt
89     0        [$21540]            |  	CICR    EQU     REGB+$0540      ; CP Interrupt Configuration
90     0        [$21544]            |  	CIPR    EQU     REGB+$0544      ; CP Interrupt Pending
91     0        [$21548]            |  	CIMR    EQU     REGB+$0548      ; CP Interrupt Mask
92     0        [$2154C]            |  	CISR    EQU     REGB+$054C      ; CP Interrupt In-service
93     0                            |  	*** Port A, B, C
94     0        [$21550]            |  	PADIR   EQU     REGB+$0550      ; Port A Data Direction Assignment
95     0        [$21552]            |  	PAPAR   EQU     REGB+$0552      ; Port A Pin Function Assignment
96     0        [$21554]            |  	PAODR   EQU     REGB+$0554      ; Port A Open Drain Assignment
97     0        [$21556]            |  	PADAT   EQU     REGB+$0556      ; Port A Data Content
98     0                            |  	*
99     0        [$216B8]            |  	PBDIR   EQU     REGB+$06B8      ; Port B Data Direction Assignment
100    0        [$216BC]            |  	PBPAR   EQU     REGB+$06BC      ; Port B Pin Function Assignment
101    0        [$216C0]            |  	PBODR   EQU     REGB+$06C0      ; Port B Open Drain Assignment
102    0        [$216C4]            |  	PBDAT   EQU     REGB+$06C4      ; Port B Data Content
103    0                            |  	*
104    0        [$21560]            |  	PCDIR   EQU     REGB+$0560      ; Port C Data Direction Assignment
105    0        [$21562]            |  	PCPAR   EQU     REGB+$0562      ; Port C Pin Assignment
106    0        [$21564]            |  	PCSO    EQU     REGB+$0564      ; Port C Special Options
107    0        [$21566]            |  	PCDAT   EQU     REGB+$0566      ; Port C Data Content
108    0        [$21568]            |  	PCINT   EQU     REGB+$0568      ; Port C Interrupt Control
109    0                            |  	*** Timer 1, 2, 3, 4
110    0        [$21580]            |  	TGCR    EQU     REGB+$0580      ; Timer Global Configuration
as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc.     May  5 1993  09:43:09      3
Source file: uart_ex1.asm

111    0                            |  	*
112    0        [$21590]            |  	TMR1    EQU     REGB+$0590      ; Timer1 Mode
113    0        [$21592]            |  	TMR2    EQU     REGB+$0592      ; Timer2 Mode
114    0        [$21594]            |  	TRR1    EQU     REGB+$0594      ; Timer1 Reference
115    0        [$21596]            |  	TRR2    EQU     REGB+$0596      ; Timer2 Reference
116    0        [$21598]            |  	TCR1    EQU     REGB+$0598      ; Timer1 Capture
117    0        [$2159A]            |  	TCR2    EQU     REGB+$059A      ; Timer2 Capture
118    0        [$2159C]            |  	TCN1    EQU     REGB+$059C      ; Timer1 Counter
119    0        [$2159E]            |  	TCN2    EQU     REGB+$059E      ; Timer2 Counter
120    0                            |  	*
121    0        [$215A0]            |  	TMR3    EQU     REGB+$05A0      ; Timer3 Mode
122    0        [$215A2]            |  	TMR4    EQU     REGB+$05A2      ; Timer4 Mode
123    0        [$215A4]            |  	TRR3    EQU     REGB+$05A4      ; Timer3 Reference
124    0        [$215A6]            |  	TRR4    EQU     REGB+$05A6      ; Timer4 Reference
125    0        [$215A8]            |  	TCR3    EQU     REGB+$05A8      ; Timer3 Capture
126    0        [$215AA]            |  	TCR4    EQU     REGB+$05AA      ; Timer4 Capture
127    0        [$215AC]            |  	TCN3    EQU     REGB+$05AC      ; Timer3 Counter
128    0        [$215AE]            |  	TCN4    EQU     REGB+$05AE      ; Timer4 Counter
129    0                            |  	*
130    0        [$215B0]            |  	TER1    EQU     REGB+$05B0      ; Timer1 Event
131    0        [$215B2]            |  	TER2    EQU     REGB+$05B2      ; Timer2 Event
132    0        [$215B4]            |  	TER3    EQU     REGB+$05B4      ; Timer3 Event
133    0        [$215B6]            |  	TER4    EQU     REGB+$05B6      ; Timer4 Event
134    0                            |  	*** CP
135    0        [$215C0]            |  	CR      EQU     REGB+$05C0      ; CP Command
136    0        [$215C4]            |  	RCCR    EQU     REGB+$05C4      ; RISC Configuration
137    0        [$215D6]            |  	RTER    EQU     REGB+$05D6      ; RISC Timer Event Register
138    0        [$215DA]            |  	RTMR    EQU     REGB+$05DA      ; RISC Timer Mask Register
139    0                            |  	* BRG 1, 2, 3, 4
140    0        [$215F0]            |  	BRGC1   EQU     REGB+$05F0      ; BRG1 Configuration
141    0        [$215F4]            |  	BRGC2   EQU     REGB+$05F4      ; BRG2 Configuration
142    0        [$215F8]            |  	BRGC3   EQU     REGB+$05F8      ; BRG3 Configuration
143    0        [$215FC]            |  	BRGC4   EQU     REGB+$05FC      ; BRG4 Configuration
144    0                            |  	*** SCC 1, 2, 3, 4
145    0                            |  	* SCC1
146    0        [$21600]            |  	GSMR_L1 EQU     REGB+$0600      ; SCC1 General Mode
147    0        [$21604]            |  	GSMR_H1 EQU     REGB+$0604      ; SCC1 General Mode
148    0        [$21608]            |  	PSMR1   EQU     REGB+$0608      ; SCC1 Protocol Specific Mode
149    0        [$2160C]            |  	TODR1   EQU     REGB+$060C      ; SCC1 Transmit On Demand
150    0        [$2160E]            |  	DSR1    EQU     REGB+$060E      ; SCC1 Data Sync
151    0        [$21610]            |  	SCCE1   EQU     REGB+$0610      ; SCC1 Event
152    0        [$21614]            |  	SCCM1   EQU     REGB+$0614      ; SCC1 Mask
153    0        [$21617]            |  	SCCS1   EQU     REGB+$0617      ; SCC1 Status
154    0                            |  	* SCC2
155    0        [$21620]            |  	GSMR_L2 EQU     REGB+$0620      ; SCC2 General Mode
156    0        [$21624]            |  	GSMR_H2 EQU     REGB+$0624      ; SCC2 General Mode
157    0        [$21628]            |  	PSMR2   EQU     REGB+$0628      ; SCC2 Protocol Specific Mode
158    0        [$2162C]            |  	TODR2   EQU     REGB+$062C      ; SCC2 Transmit On Demand
159    0        [$2162E]            |  	DSR2    EQU     REGB+$062E      ; SCC2 Data Sync
160    0        [$21630]            |  	SCCE2   EQU     REGB+$0630      ; SCC2 Event
161    0        [$21634]            |  	SCCM2   EQU     REGB+$0634      ; SCC2 Mask
162    0        [$21637]            |  	SCCS2   EQU     REGB+$0637      ; SCC2 Status
163    0                            |  	* SCC3
164    0        [$21640]            |  	GSMR_L3 EQU     REGB+$0640      ; SCC3 General Mode
165    0        [$21644]            |  	GSMR_H3 EQU     REGB+$0644      ; SCC3 General Mode
as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc.     May  5 1993  09:43:09      4
Source file: uart_ex1.asm

166    0        [$21648]            |  	PSMR3   EQU     REGB+$0648      ; SCC3 Protocol Specific Mode
167    0        [$2164C]            |  	TODR3   EQU     REGB+$064C      ; SCC3 Transmit On Demand
168    0        [$2164E]            |  	DSR3    EQU     REGB+$064E      ; SCC3 Data Sync
169    0        [$21650]            |  	SCCE3   EQU     REGB+$0650      ; SCC3 Event
170    0        [$21654]            |  	SCCM3   EQU     REGB+$0654      ; SCC3 Mask
171    0        [$21657]            |  	SCCS3   EQU     REGB+$0657      ; SCC3 Status
172    0                            |  	* SCC4
173    0        [$21660]            |  	GSMR_L4 EQU     REGB+$0660      ; SCC4 General Mode
174    0        [$21664]            |  	GSMR_H4 EQU     REGB+$0664      ; SCC4 General Mode
175    0        [$21668]            |  	PSMR4   EQU     REGB+$0668      ; SCC4 Protocol Specific Mode
176    0        [$2166C]            |  	TODR4   EQU     REGB+$066C      ; SCC4 Transmit On Demand
177    0        [$2166E]            |  	DSR4    EQU     REGB+$066E      ; SCC4 Data Sync
178    0        [$21670]            |  	SCCE4   EQU     REGB+$0670      ; SCC4 Event
179    0        [$21674]            |  	SCCM4   EQU     REGB+$0674      ; SCC4 Mask
180    0        [$21677]            |  	SCCS4   EQU     REGB+$0677      ; SCC4 Status
181    0                            |  	*** SMC 1, 2
182    0        [$21682]            |  	SMCMR1  EQU     REGB+$0682      ; SMC1 Mode
183    0        [$21686]            |  	SMCE1   EQU     REGB+$0686      ; SMC1 Event
184    0        [$2168A]            |  	SMCM1   EQU     REGB+$068A      ; SMC1 Mask
185    0                            |  	*
186    0        [$21692]            |  	SMCMR2  EQU     REGB+$0692      ; SMC2 Mode
187    0        [$21696]            |  	SMCE2   EQU     REGB+$0696      ; SMC2 Event
188    0        [$2169A]            |  	SMCM2   EQU     REGB+$069A      ; SMC2 Mask
189    0                            |  	*** SPI
190    0        [$216A0]            |  	SPMODE  EQU     REGB+$06A0      ; SPI Mode
191    0        [$216A6]            |  	SPIE    EQU     REGB+$06A6      ; SPI Event
192    0        [$216AA]            |  	SPIM    EQU     REGB+$06AA      ; SPI Mask
193    0        [$216AD]            |  	SPCOM   EQU     REGB+$06AD      ; SPI Command
194    0                            |  	*** PIP
195    0        [$216B2]            |  	PIPC    EQU     REGB+$06B2      ; PIP Configuration
196    0        [$216B6]            |  	PTRR    EQU     REGB+$06B6      ; PIP Timing Parameter
197    0                            |  	*** Serial Interface
198    0        [$216E0]            |  	SIMODE  EQU     REGB+$06E0      ; SI Mode
199    0        [$216E4]            |  	SIGMR   EQU     REGB+$06E4      ; SI Global Mode
200    0        [$216E6]            |  	SISTR   EQU     REGB+$06E6      ; SI Status
201    0        [$216E7]            |  	SICMR   EQU     REGB+$06E7      ; SI Command
202    0        [$216EC]            |  	SICR    EQU     REGB+$06EC      ; SI Clock Routing
203    0        [$216F0]            |  	SIRP    EQU     REGB+$06F0      ; SI RAM Pointer
204    0        [$21700]            |  	SIRAM   EQU     REGB+$0700      ; SI Routing RAM
205    0                            |  	
206    0                            |  	************************ END of SIM/CPM Register MAP *******************
207    0                            |  	
208    0                            |  	************************ SCC Parameters ********************************
209    0                            |  	****** SCC1
210    0        [$20C00]            |  	RBASE1  EQU     SCC1PB+$000     ; SCC1 RX BD Base Address
211    0        [$20C02]            |  	TBASE1  EQU     SCC1PB+$002     ; SCC1 TX BD Base Address
212    0        [$20C04]            |  	RFCR1   EQU     SCC1PB+$004     ; SCC1 RX Function Code
213    0        [$20C05]            |  	TFCR1   EQU     SCC1PB+$005     ; SCC1 TX Function Code
214    0        [$20C06]            |  	MRBLR1  EQU     SCC1PB+$006     ; SCC1 MAX Buffer Length - RX
215    0        [$20C08]            |  	RSTATE1 EQU     SCC1PB+$008     ; SCC1 RX Internal State
216    0        [$20C10]            |  	RBPRT1  EQU     SCC1PB+$010     ; SCC1 RX BD Pointer
217    0        [$20C18]            |  	TSTATE1 EQU     SCC1PB+$018     ; SCC1 TX Internal State
218    0        [$20C20]            |  	TBPRT1  EQU     SCC1PB+$020     ; SCC1 TX BD Pointer
219    0        [$20C28]            |  	RCRC1   EQU     SCC1PB+$028     ; SCC1 Temp Receive CRC
220    0        [$20C2C]            |  	TCRC1   EQU     SCC1PB+$02C     ; SCC1 Temp Transmit CRC
as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc.     May  5 1993  09:43:09      5
Source file: uart_ex1.asm

221    0                            |  	****** SCC2
222    0        [$20D00]            |  	RBASE2  EQU     SCC2PB+$000     ; SCC2 RX BD Base Address
223    0        [$20D02]            |  	TBASE2  EQU     SCC2PB+$002     ; SCC2 TX BD Base Address
224    0        [$20D04]            |  	RFCR2   EQU     SCC2PB+$004     ; SCC2 RX Function Code
225    0        [$20D05]            |  	TFCR2   EQU     SCC2PB+$005     ; SCC2 TX Function Code
226    0        [$20D06]            |  	MRBLR2  EQU     SCC2PB+$006     ; SCC2 MAX Buffer Length - RX
227    0        [$20D08]            |  	RSTATE2 EQU     SCC2PB+$008     ; SCC2 RX Internal State
228    0        [$20D10]            |  	RBPRT2  EQU     SCC2PB+$010     ; SCC2 RX BD Pointer
229    0        [$20D18]            |  	TSTATE2 EQU     SCC2PB+$018     ; SCC2 TX Internal State
230    0        [$20D20]            |  	TBPRT2  EQU     SCC2PB+$020     ; SCC2 TX BD Pointer
231    0        [$20D28]            |  	RCRC2   EQU     SCC2PB+$028     ; SCC2 Temp Receive CRC
232    0        [$20D2C]            |  	TCRC2   EQU     SCC2PB+$02C     ; SCC2 Temp Transmit CRC
233    0                            |  	****** SCC3
234    0        [$20E00]            |  	RBASE3  EQU     SCC3PB+$000     ; SCC3 RX BD Base Address
235    0        [$20E02]            |  	TBASE3  EQU     SCC3PB+$002     ; SCC3 TX BD Base Address
236    0        [$20E04]            |  	RFCR3   EQU     SCC3PB+$004     ; SCC3 RX Function Code
237    0        [$20E05]            |  	TFCR3   EQU     SCC3PB+$005     ; SCC3 TX Function Code
238    0        [$20E06]            |  	MRBLR3  EQU     SCC3PB+$006     ; SCC3 MAX Buffer Length - RX
239    0        [$20E08]            |  	RSTATE3 EQU     SCC3PB+$008     ; SCC3 RX Internal State
240    0        [$20E10]            |  	RBPRT3  EQU     SCC3PB+$010     ; SCC3 RX BD Pointer
241    0        [$20E18]            |  	TSTATE3 EQU     SCC3PB+$018     ; SCC3 TX Internal State
242    0        [$20E20]            |  	TBPRT3  EQU     SCC3PB+$020     ; SCC3 TX BD Pointer
243    0        [$20E28]            |  	RCRC3   EQU     SCC3PB+$028     ; SCC3 Temp Receive CRC
244    0        [$20E2C]            |  	TCRC3   EQU     SCC3PB+$02C     ; SCC3 Temp Transmit CRC
245    0                            |  	****** SCC4
246    0        [$20F00]            |  	RBASE4  EQU     SCC4PB+$000     ; SCC4 RX BD Base Address
247    0        [$20F02]            |  	TBASE4  EQU     SCC4PB+$002     ; SCC4 TX BD Base Address
248    0        [$20F04]            |  	RFCR4   EQU     SCC4PB+$004     ; SCC4 RX Function Code
249    0        [$20F05]            |  	TFCR4   EQU     SCC4PB+$005     ; SCC4 TX Function Code
250    0        [$20F06]            |  	MRBLR4  EQU     SCC4PB+$006     ; SCC4 MAX Buffer Length - RX
251    0        [$20F08]            |  	RSTATE4 EQU     SCC4PB+$008     ; SCC4 RX Internal State
252    0        [$20F10]            |  	RBPRT4  EQU     SCC4PB+$010     ; SCC4 RX BD Pointer
253    0        [$20F18]            |  	TSTATE4 EQU     SCC4PB+$018     ; SCC4 TX Internal State
254    0        [$20F20]            |  	TBPRT4  EQU     SCC4PB+$020     ; SCC4 TX BD Pointer
255    0        [$20F28]            |  	RCRC4   EQU     SCC4PB+$028     ; SCC4 Temp Receive CRC
256    0        [$20F2C]            |  	TCRC4   EQU     SCC4PB+$02C     ; SCC4 Temp Transmit CRC
257    0        [$20F30]            |  	CRC_C4  EQU     SCC4PB+$030     ; SCC4 CRC Constant Total-Transparent
258    0        [$20F34]            |  	CRC_P4  EQU     SCC4PB+$034     ; SCC4 CRC Preset Total-Transparent
259    0                            |  	****** SMC1 => SMCA, simplify assembly coding
260    0        [$20E80]            |  	RBASEA  EQU     SMC1PB+$000     ; SMC1 RX BD Base Address
261    0        [$20E82]            |  	TBASEA  EQU     SMC1PB+$002     ; SMC1 TX BD Base Address
262    0        [$20E84]            |  	RFCRA   EQU     SMC1PB+$004     ; SMC1 RX Function Code
263    0        [$20E85]            |  	TFCRA   EQU     SMC1PB+$005     ; SMC1 TX Function Code
264    0        [$20E86]            |  	MRBLRA  EQU     SMC1PB+$006     ; SMC1 MAX Buffer Length - RX
265    0        [$20E88]            |  	RSTATEA EQU     SMC1PB+$008     ; SMC1 RX Internal State
266    0        [$20E90]            |  	RBPRTA  EQU     SMC1PB+$010     ; SMC1 RX BD Pointer
267    0        [$20E98]            |  	TSTATEA EQU     SMC1PB+$018     ; SMC1 TX Internal State
268    0        [$20EA0]            |  	TBPRTA  EQU     SMC1PB+$020     ; SMC1 TX BD Pointer
269    0                            |  	****** SMC1 => SMCB
270    0        [$20F80]            |  	RBASEB  EQU     SMC2PB+$000     ; SMC2 RX BD Base Address
271    0        [$20F82]            |  	TBASEB  EQU     SMC2PB+$002     ; SMC2 TX BD Base Address
272    0        [$20F84]            |  	RFCRB   EQU     SMC2PB+$004     ; SMC2 RX Function Code
273    0        [$20F85]            |  	TFCRB   EQU     SMC2PB+$005     ; SMC2 TX Function Code
274    0        [$20F86]            |  	MRBLRB  EQU     SMC2PB+$006     ; SMC2 MAX Buffer Length - RX
275    0        [$20F88]            |  	RSTATEB EQU     SMC2PB+$008     ; SMC2 RX Internal State
as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc.     May  5 1993  09:43:09      6
Source file: uart_ex1.asm

276    0        [$20F90]            |  	RBPRTB  EQU     SMC2PB+$010     ; SMC2 RX BD Pointer
277    0        [$20F98]            |  	TSTATEB EQU     SMC2PB+$018     ; SMC2 TX Internal State
278    0        [$20FA0]            |  	TBPRTB  EQU     SMC2PB+$020     ; SMC2 TX BD Pointer
279    0                            |  	
280    0                            |  	
281    0                            |  	
282    0                            |  	************************** Specific Parameters ******************************
283    0                            |  	* SCC2, HDLC Specific Parameters
284    0        [$20D34]            |  	C_MASK2 EQU     SCC2PB+$34      ; SCC2 CRC Constant
285    0        [$20D38]            |  	C_PRES2 EQU     SCC2PB+$38      ; SCC2 CRC Preset
286    0        [$20D3C]            |  	DISFC2  EQU     SCC2PB+$3C      ; SCC2 Discard Frame Counter
287    0        [$20D3E]            |  	CRCEC2  EQU     SCC2PB+$3E      ; SCC2 CRC Error Counter
288    0        [$20D40]            |  	ABTSC2  EQU     SCC2PB+$40      ; SCC2 Abort Sequence Counter
289    0        [$20D42]            |  	NMARC2  EQU     SCC2PB+$42      ; SCC2 NonMatch Addr Rx Counter
290    0        [$20D44]            |  	RETRC2  EQU     SCC2PB+$44      ; SCC2 Frame ReTRansmit Counter
291    0        [$20D46]            |  	MFLR2   EQU     SCC2PB+$46      ; SCC2 Max Frame Length Register
292    0        [$20D48]            |  	MAXCNT2 EQU     SCC2PB+$48      ; SCC2 MAX length Counter
293    0        [$20D4A]            |  	RFTHR2  EQU     SCC2PB+$4A      ; SCC2 Receive Frames THreshold
294    0        [$20D4C]            |  	RFCNT2  EQU     SCC2PB+$4C      ; SCC2 Receive Frames Count
295    0        [$20D4E]            |  	HMASK2  EQU     SCC2PB+$4E      ; SCC2 Frame Address Mask (U-D)
296    0        [$20D50]            |  	HADDR12 EQU     SCC2PB+$50      ; SCC2 Frame Address 1
297    0        [$20D52]            |  	HADDR22 EQU     SCC2PB+$52      ; SCC2 Frame Address 2
298    0        [$20D54]            |  	HADDR32 EQU     SCC2PB+$54      ; SCC2 Frame Address 3
299    0        [$20D56]            |  	HADDR42 EQU     SCC2PB+$56      ; SCC2 Frame Address 4
300    0                            |  	
301    0                            |  	* SCC4, UART Specific Parameters
302    0        [$20F38]            |  	MAXIDL4 EQU     SCC4PB+$38      ; SCC4 MAX IDLe cchars
303    0        [$20F3A]            |  	IDLC4   EQU     SCC4PB+$3A      ; SCC4 temp IDLe Counter
304    0        [$20F3C]            |  	BRKCR4  EQU     SCC4PB+$3C      ; SCC4 BReaK Count Register (TX)
305    0        [$20F3E]            |  	PAREC4  EQU     SCC4PB+$3E      ; SCC4 Parity Error Counter (RX)
306    0        [$20F40]            |  	FRMER4  EQU     SCC4PB+$40      ; SCC4 Framing Error Counter (RX)
307    0        [$20F42]            |  	NOSEC4  EQU     SCC4PB+$42      ; SCC4 Noise Counter (RX)
308    0        [$20F44]            |  	BRKEC4  EQU     SCC4PB+$44      ; SCC4 BReaK Condition Counter (RX)
309    0        [$20F46]            |  	BRKLN4  EQU     SCC4PB+$46      ; SCC4 Last BReaK Length (RX)
310    0        [$20F48]            |  	UADDR14 EQU     SCC4PB+$48      ; SCC4 UART Address Character 1
311    0        [$20F4A]            |  	UADDR24 EQU     SCC4PB+$4A      ; SCC4 UART Address Character 2
312    0        [$20F4C]            |  	RETMP4  EQU     SCC4PB+$4C      ; SCC4 Temp storage
313    0        [$20F4E]            |  	TOSEQ4  EQU     SCC4PB+$4E      ; SCC4 TX out of sequence Character
314    0        [$20F50]            |  	CCHAR14 EQU     SCC4PB+$50      ; SCC4 Control Character 1
315    0        [$20F52]            |  	CCHAR24 EQU     SCC4PB+$52      ; SCC4 Control Character 2
316    0        [$20F54]            |  	CCHAR34 EQU     SCC4PB+$54      ; SCC4 Control Character 3
317    0        [$20F56]            |  	CCHAR44 EQU     SCC4PB+$56      ; SCC4 Control Character 4
318    0        [$20F58]            |  	CCHAR54 EQU     SCC4PB+$58      ; SCC4 Control Character 5
319    0        [$20F5A]            |  	CCHAR64 EQU     SCC4PB+$5A      ; SCC4 Control Character 6
320    0        [$20F5C]            |  	CCHAR74 EQU     SCC4PB+$5C      ; SCC4 Control Character 7
321    0        [$20F5E]            |  	CCHAR84 EQU     SCC4PB+$5E      ; SCC4 Control Character 8
322    0        [$20F60]            |  	RCCM4   EQU     SCC4PB+$60      ; SCC4 RX Control Character Mask
323    0        [$20F62]            |  	RCCR4   EQU     SCC4PB+$62      ; SCC4 RX Control Character
324    0        [$20F64]            |  	RLBC4   EQU     SCC4PB+$64      ; SCC4 RX Last Break Character
325    0                            |  	
326    0                            |  	* SCC3, BISYNC Specific Parameters
327    0        [$20E38]            |  	CRCC3   EQU     SCC3PB+$38      ; SCC3 CRC Constant Temp Value
328    0        [$20E3A]            |  	PRCRC3  EQU     SCC3PB+$3A      ; SCC3 Preset RX CRC16/LRC
329    0        [$20E3C]            |  	PTCRC3  EQU     SCC3PB+$3C      ; SCC3 Preset TX CRC16/LRC
330    0        [$20E3E]            |  	PAREC3  EQU     SCC3PB+$3E      ; SCC3 Parity Error Counter (RX)
as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc.     May  5 1993  09:43:09      7
Source file: uart_ex1.asm

331    0        [$20E40]            |  	BSYNC3  EQU     SCC3PB+$40      ; SCC3 BISYNC SYNC Character
332    0        [$20E42]            |  	BIDLE3  EQU     SCC3PB+$42      ; SCC3 BISYNC IDLE Character
333    0        [$20E44]            |  	CCHAR13 EQU     SCC3PB+$44      ; SCC3 Control Character 1
334    0        [$20E46]            |  	CCHAR23 EQU     SCC3PB+$46      ; SCC3 Control Character 2
335    0        [$20E48]            |  	CCHAR33 EQU     SCC3PB+$48      ; SCC3 Control Character 3
336    0        [$20E4A]            |  	CCHAR43 EQU     SCC3PB+$4A      ; SCC3 Control Character 4
337    0        [$20E4C]            |  	CCHAR53 EQU     SCC3PB+$4C      ; SCC3 Control Character 5
338    0        [$20E4E]            |  	CCHAR63 EQU     SCC3PB+$4E      ; SCC3 Control Character 6
339    0        [$20E50]            |  	CCHAR73 EQU     SCC3PB+$50      ; SCC3 Control Character 7
340    0        [$20E52]            |  	CCHAR83 EQU     SCC3PB+$52      ; SCC3 Control Character 8
341    0        [$20E54]            |  	RCCM3   EQU     SCC3PB+$54      ; SCC3 RX Control Character Mask
342    0                            |  	
343    0                            |  	* SMC1, UART Specific Parameters
344    0        [$20EA8]            |  	MAXIDLA EQU     SMC1PB+$28      ; SMC1 MAX IDLe cchars
345    0        [$20EAA]            |  	IDLCA   EQU     SMC1PB+$2A      ; SMC1 temp IDLe Counter
346    0        [$20EAC]            |  	BRKLA   EQU     SMC1PB+$2C      ; SMC1 last Received BReaK char length
347    0        [$20EAE]            |  	BRKECA  EQU     SMC1PB+$2E      ; SMC1 receive BReaK Condition Counter
348    0        [$20EB0]            |  	BRKCRA  EQU     SMC1PB+$30      ; SMC1 BReaK Count Register (TX)
349    0                            |  	
350    0                            |  	
351    0                            |  	
352    0                         >  |  	        ORG     INIT
353    402000                       |  	
354    402000   23FCFFFFFFFF000215  |  	        MOVE.L  #$FFFFFFFF,CIPR ; clear IRQ pending register
                44                  |
355    40200A                       |  	
356    40200A   33FC00C000021552    |  	        MOVE.W  #$00C0,PAPAR    ; port A pin 6+7 - dedicated function (RXD,TXD)
357    402012   427900021554        |  	        CLR.W   PAODR           ; port A pin 6+7 - I/O outputs
358    402018   427900021550        |  	        CLR.W   PADIR           ; port A pin 6+7 - inputs
359    40201E                       |  	
360    40201E   33FC07500002151E    |  	        MOVE.W  #$0750,SDCR     ; interrupt service mask = 7, arbit. ID = 5
361    402026                       |  	
362    402026   33FC000400021562    |  	        MOVE.W  #$0004,PCPAR    ; port C select RTS4,CTS4,CD4
363    40202E   427900021560        |  	        CLR.W   PCDIR           ; port C select RTS4,CTS4,CD4
364    402034   33FC0C0000021564    |  	        MOVE.W  #$0C00,PCSO     ; port C select RTS4,CTS4,CD4
365    40203C                       |  	
366    40203C                       |  	
367    40203C   23FC00010144000215  |  	        MOVE.L  #$010144,BRGC1  ; set BRG1 to baud rate 9600bits/s
                F0                  |
368    402046   42B9000216EC        |  	        CLR.L   SICR            ; route brg1 to scc4 and select NMSI pins
369    40204C                       |  	
370    40204C   33FC000000020F00    |  	        MOVE.W  #$0000,RBASE4   ; receive buffer dis. base address = 20000
371    402054   33FC000800020F02    |  	        MOVE.W  #$0008,TBASE4   ; trans. buffer dis. base address = 20008
372    40205C   13FC001500020F04    |  	        MOVE.B  #$15,RFCR4      ; MOT=1(MSByte first), RX function code = 0101
373    402064   13FC001500020F05    |  	        MOVE.B  #$15,TFCR4      ; MOT=1(MSByte first), TX function code = 0101
374    40206C   33FC001000020F06    |  	        MOVE.W  #$0010,MRBLR4   ; max. bytes per receiver (16)
375    402074                       |  	
376    402074   33FC00C1000215C0    |  	        MOVE.W  #$00C1,CR       ; initialize transmit and receive parameter
377    40207C                       |  	*                               ; in the parameter RAM of SCC4
378    40207C                       |  	
379    40207C                       |  	
380    40207C   33FC000000020F38    |  	        MOVE.W  #$0000,MAXIDL4  ; disable idle funktion
381    402084   33FC000100020F3C    |  	        MOVE.W  #$0001,BRKCR4   ; STOP TRANS. command will issue 1 break chara.
382    40208C   33FC000000020F3E    |  	        MOVE.W  #$0,PAREC4
383    402094   33FC000000020F40    |  	        MOVE.W  #$0,FRMER4
as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc.     May  5 1993  09:43:09      8
Source file: uart_ex1.asm

384    40209C   33FC000000020F42    |  	        MOVE.W  #$0,NOSEC4
385    4020A4   33FC000000020F44    |  	        MOVE.W  #$0,BRKEC4
386    4020AC   33FC000000020F48    |  	        MOVE.W  #$0,UADDR14
387    4020B4   33FC000000020F4A    |  	        MOVE.W  #$0,UADDR24
388    4020BC   33FC000000020F4E    |  	        MOVE.W  #$0,TOSEQ4
389    4020C4   33FC800000020F50    |  	        MOVE.W  #$8000,CCHAR14
390    4020CC   33FC800000020F52    |  	        MOVE.W  #$8000,CCHAR24
391    4020D4   33FC800000020F54    |  	        MOVE.W  #$8000,CCHAR34
392    4020DC   33FC800000020F56    |  	        MOVE.W  #$8000,CCHAR44
393    4020E4   33FC800000020F58    |  	        MOVE.W  #$8000,CCHAR54
394    4020EC   33FC800000020F5A    |  	        MOVE.W  #$8000,CCHAR64
395    4020F4   33FC800000020F5C    |  	        MOVE.W  #$8000,CCHAR74
396    4020FC   33FC800000020F5E    |  	        MOVE.W  #$8000,CCHAR84
397    402104   33FCC0FF00020F60    |  	        MOVE.W  #$C0FF,RCCM4
398    40210C                       |  	
399    40210C   33FCB00000020000    |  	        MOVE.W  #$B000,RXBD            ; RxBD status Reg.
400    402114   33FC000000020002    |  	        MOVE.W  #$0000,RXBD+$0002      ; RxBD data length REG.
401    40211C   23FC00404000000200  |  	        MOVE.L  #$00404000,RXBD+$0004  ; pointer to receive data at
                04                  |
402    402126                       |  	*                                      ; DRAM address 404000
403    402126                       |  	
404    402126   33FCB00000020008    |  	        MOVE.W  #$B000,TXBD            ; TxBD status Reg.
405    40212E   33FC00100002000A    |  	        MOVE.W  #$0010,TXBD+$0002      ; data length Reg.
406    402136   23FC00404100000200  |  	        MOVE.L  #$00404100,TXBD+$0004  ; pointer to transmit data at
                0C                  |
407    402140                       |  	*                                      ; DRAM address 404100
408    402140                       |  	
409    402140   33FCFFFF00021670    |  	        MOVE.W  #$FFFF,SCCE4           ; clear SCC4 event register
410    402148   33FC000300021674    |  	        MOVE.W  #$0003,SCCM4           ; enable TX and Rx interrupts
411    402150                       |  	
412    402150                       |  	
413    402150   23FC00E4FF00000215  |  	        MOVE.L  #$00E4FF00,CICR        ; IRQ conf. reg.
                40                  |
414    40215A   23FC08000000000215  |  	        MOVE.L  #$08000000,CIMR        ; allow scc4 systeminterrupt
                48                  |
415    402164                       |  	
416    402164   23FC00000020000216  |  	        MOVE.L  #$00000020,GSMR_H4     ; Rx FIFO set to 8 bit wide
                64                  |
417    40216E                       |  	
418    40216E                       |  	
419    40216E                       |  	
420    40216E                       |  	* if you use the next line, you set up the SCC to loopback mode            *
421    40216E                       |  	
422    40216E                       |  	*       MOVE.L  #$00028044,GSMR_L4     ; TDCR ='10', txclk is 16* clock mode
423    40216E                       |  	*                                      ; RDCR ='10', rxclk is 16* clock mode
424    40216E                       |  	*                                      ; local loopback mode
425    40216E                       |  	*                                      ; channel protocol mode = UART
426    40216E                       |  	
427    40216E   23FC00028004000216  |  	        MOVE.L  #$00028004,GSMR_L4     ; TDCR ='10', txclk is 16* clock mode
                60                  |
428    402178                       |  	*                                      ; RDCR ='10', rxclk is 16* clock mode
429    402178                       |  	*                                      ; channel protocol mode = UART
430    402178                       |  	
431    402178                       |  	
432    402178   33FCB00000021668    |  	        MOVE.W  #$B000,PSMR4           ; set automatic flow control
as68k version 3.69.1.1 (c) 1992 Intermetrics, Inc.     May  5 1993  09:43:09      9
Source file: uart_ex1.asm

433    402180                       |  	*                                      ; character length set to 8 bits
434    402180                       |  	
435    402180   4E71                |  	        NOP                            ; this is a point where you can
436    402182                       |  	*                                      ; put a breakpoint, if you want.
437    402182                       |  	*                                      ; the SCC is setup and the next
438    402182                       |  	*                                      ; instruction will enable the trans-
439    402182                       |  	*                                      ; mission.
440    402182                       |  	
441    402182                       |  	*       MOVE.L  #$00028074,GSMR_L4     ; enable transmitter and receiver
442    402182                       |  	*                                      ; in loopback mode
443    402182                       |  	
444    402182   23FC00028034000216  |  	        MOVE.L  #$00028034,GSMR_L4     ; enable transmitter and receiver
                60                  |
445    40218C                       |  	
446    40218C                       |  	*       MOVE.L  #$00028044,GSMR_L4     ; stop transmitter and receiver
447    40218C                       |  	
448    40218C   23FC00028004000216  |  	        MOVE.L  #$00028004,GSMR_L4     ; stop transmitter and receiver
                60                  |
449    402196                       |  	
450    402196                       |  	
451    402196                       |  	        END
