68HC05 Instruction Set — Part 7
BIH branch if IRQ pin is high BIL branch if IRQ pin is low BRA branch always BRN branch never BSR branch to subroutine and save return address on stack
BCLR clear the designated memory bit BSET set the designated memory bit BRCLR branch if the designated memory bit is clear BRSET branch if the designated memory bit is set
Notes:
These “other” branch instructions do not examine bits in the condition code register to change program flow. BIH and BIL, in particular, test the state of the actual IRQ pin, not the condition code register interrupt mask (I) bit.
BRN is useful as a three clock cycle no operation instruction. The actual NOP instruction executes in two clock cycles and has a different opcode.
The single bit operations allow setting and clearing of and branching on the set or clear states of single bits in a byte operand. These instructions use the direct addressing mode only and can operand on any bit in the first 256 locations of memory (i.e. internal RAM and peripheral control registers).
The BCLR and BSET instructions each have eight opcodes, one for each bit in a byte. BCLR and BSET require two bytes of storage and execute in five clock cycles which makes them the most memory and time efficient way to clear or set a bit. The same operations using the LDA, AND/ORA, and STA instructions require six bytes and nine clock cycles.
BRCLR and BRSET are similarly efficient, needing only three bytes and five cycles for an operation that would otherwise require six bytes and eight cycles if using a sequence of LDA, AND/ORA, and BEQ/BNE instructions.