16-Bit Timer Overflow
Notes:
All functions of the 16-bit timer are related to the 16-bit counter which serves as its time base.
The counter can be read from two locations, both of which return the same data. A read of the timer register high (TRH) byte or the alternate timer register high (ATRH) byte returns the high byte of the 16-bit counter and latches the low byte of the 16-bit counter in a buffer until it can be read from TRL or ATRL. Repetitive reads of the high byte will not change the low byte in the buffer until it is read.
The 16-bit counter increments once every four internal clock cycles, and upon reaching $FFFF, it rolls over to $0000. This event sets the timer overflow flag (TOF) in the timer status register (TSR) and generates a timer overflow interrupt request if the timer overflow interrupt enable (TOIE) bit in the timer control register (TCR) is set.
The TOF bit in TSR remains set unless explicitly cleared. A read of TSR, followed by a read of TRL, clears TOF. The same sequence will not clear TOF if ATRL is read in place of TRL. This allows the counter to be read at all times (from ATRH and ATRL) without the possibility of missing a timer overflow interrupt.