16-Bit Timer Output Compare
Notes:
Output compare is essentially a method for generating delays, because it allows future events to be synchronized to the current value of the 16-bit timer counter.
The output compare high (OCRH) and low (OCRL) registers hold the value that the 16-bit timer counter will match at some point in the future. When writing to the output compare registers, first write data to OCRH. This prevents a match from occurring until OCRL is written.
When a match occurs, the TCMP pin will be driven to the level specified by the OLVL bit in the timer control register (TCR), and the output compare flag (OCF) bit in the timer status register (TSR) will be set. An interrupt will also be generated if the output compare interrupt enable (OCIE) bit in TCR is set. A read of TSR, followed by a read of or write to OCRL, clears OCF.
The EKG signal that appears across the handlebar contacts must be sampled at a fixed frequency in order to make accurate pulse calculations. Analog-to-digital conversion of the EKG waveform occurs during the service routine of a 100 Hz interrupt generated by the output compare hardware. By finding two adjacent peaks of similar amplitude on the EKG wave, the time between two heart beats is known in hundredths of a second and can be converted to a pulse rate in beats per minute.