An Enhanced SCI — The SCI+
In addition to the capabilities of the standard SCI, the enhanced serial communications interface (SCI+) supports…
? Separate transmitter and receiver baud rates
? Output of the transmitter clock on the dedicated SCLK pin
? SCLK phase and polarity control
? Output-only, least significant bit first, synchronous transfers
The SCI+ essentially adds a simple, master mode, SPI-like, synchronous transfer capability to the standard SCI’s UART features.
Notes:
As noted above, the SCI+ can perform simple, output-only, synchronous transmissions in addition to its standard UART functions.
Like the regular SCI, the SCI+ has a prescaler that divides the internal MCU clock by 1, 3, 4, or 13. Three control bits on the standard SCI further divide this prescaler output by 1, 2, 4, 8, 16, 32, 64, or 128 to derive the transmitter and receiver clocks. On the SCI+, two sets of these bits provide the same division factors and allow independent baud rate selection for both the receiver and transmitter.
In addition to its asynchronous transfer capability, the SCI+ can transmit data synchronously by using the transmitter clock signal present on the dedicated SCLK pin. The synchronous transfer mode of the SCI+ is not, however, fully SPI-compliant. While it does have the obligatory CPOL and CPHA bits to control the polarity and phase of the shift clock on SCLK, the SCI+ performs all trannsfers in the same order as a UART — LSB first — which is opposite that used by the SPI.
Nonetheless, data placed in the proper bit order is transmitted in the same fashion on the SCI+ as it is on the SPI. Additionally, because a single data register is used for all transfers, the SCI+ can use 8- or 9-bit data words for synchronous as well as asynchronous transfers.