Pulse Length Modulation Timer
Notes:
The pulse length modulation (PLM) timer has two channels, each with an 8-bit, buffered duty cycle register, an 8-bit comparator, zero detection circuitry, a slow/fast rate multiplexer, and a latch that drives an associated output pin.
PLM waveforms are output at one of two fixed frequencies and are active high for a user-specified length of time. A rate selection multiplexer allows each channel to choose a fast or slow 8-bit time base consisting, respectively, of bits [7:0] or [11:4] of the counter associated with the 16-bit timer subsystem.
In fast and slow modes, one count of the 8-bit time base is, respectively, 4 and 64 internal MCU clock cycles. The resulting output waveform periods are likewise 4 ? 256 = 1024 and 64 ? 256 = 16384 internal MCU clock cycles. Each PLM duty cycle register, just as its associated time base, is 8 bits wide.
Once a time base and duty cycle are selected, a PLM channel operates as follows. Starting at $00, the 8-bit time base increments at the user-specified fast or slow rate. When a non-zero duty cycle is in effect, the channel output pin is driven high and remains there until the duty cycle register value matches that of the 8-bit time base. The comparator detects this match and clears the output control latch, driving the associated PLM pin low. The waveform remains low until the 8-bit time base rolls over from $FF to $00, and the zero detection circuit sets the output control latch, again driving the PLM pin high.