FR500 Series
Table
MB93501
DESCRIPTION

The FR500 architecture integrates control functionality performed by MPU and media-rich processing functionality with powerful arithmetic for floating-point and fixed-point operations. The FR500 offers a four-slot VLIW that unifies media(M), floating-point(F), and integer(I) instructions.

4-slot VLIW FR500

The features of the first implementation of the FR-V family, FR500 core, are described below. The FR500 core achieves high system performance and low power consumption at low cost, taking full advantage of the powerful parallel processing capabilities of the VLIW.

FEATURES


 Integer Unit 532MIPS

One-cycle latency except MULT(2 cycles) and DIV(19 cycles)

Two 64 bit data load instructions per cycle

Two-branch instructions packed in any slots of a VLIW

Cache

16kB for instruction and data

Four way set-associative

Preloading with cache-line lock control

Non-blocking

Floating Point Unit 1064MFLOPS

Three-cycle latency except SQRT: (15 cycles) and DIV (10 cycles)

Media Unit: 4,256MOPS:

One-cycle accumulation for MAC, otherwise 2 cycle latency

Frequency

266MHz 0.18 µm CMOS