Question: The data book (page 8-6) explains that the internal PLL is disabled as soon as the internal oscillator runs. This implies that you can only use an external crystal with the divide-by-2 option. My customer is using a 10Mhz external crystal connected between X1 and X2/CLKIN with DIV1=0 and DIV2=1. Instead of getting a CLKOUT of 5Mhz, he gets a CLKOUT of 20 MHz. This seems to indicate that the internal PLL ( *2) is active ! Could you tell me if the user"s guide is correct ? If yes then could you give me the reason of the behavior of the CLKOUT signal ?

Answer: The internal oscillator of the "F206 is not disabled in any of the PLL modes. Section 8-2 of the UG is incorrect, and will be changed in the next revision of the document.

Note: If the on-chip oscillator is used with the PLL enabled, both the oscillator start-up time and PLL lock-up time must be considered during power-up. In other words, the 2500 cycles for PLL lock begin after the Osc stabilizes, and the RESET pin should be held low for the entire time.