The TVP3409 RAMDAC utilizes a low cost DRAM frame buffer to reduce overall system cost. The 24-bit packed pixel mode allows maximum use of controller to RAMDAC bandwidth. This enables much higher screen refresh rate in 800 x 600 x 24 mode and makes 1024 x 768 x 24 mode possible with a 3 M Byte frame buffer.
The TVP3409 is highly integrated, featuring triple high-speed 8-bit DACs, three 256-by-8 color lookup tables and a programmable pixel multiplexing interface. In addition to these advanced RAMDAC features, the device also integrates dual frequency synthesis PLLs thereby reducing component count, board space, and electrical emission. The PLLs are used to generate the controller's memory and video clocks at frequencies up to 85 MHz.
The TVP3409 also features a clock multiplier PLL which multiplies the controller PCLK to obtain the pixel clock at frequencies up to 170 MHz. The TVP3409 also shares a common register format with the 8-bit ATT20C498/499, allowing software compatibility and an easy migration path to 16-bit graphics designs.
The TVP3409 is compatible with most industry standard graphics controllers. The device is available in a 68-pin PLCC package, and specified for operation from 0ºC to 70ºC.
Vol 14, December, 1995
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