TMS320C54x features are aimed at maximizing the DSPs' performance in wireless communications systems such as voice coding and decoding:
Features Benefits
Integrated Viterbi accelerator Reduces Viterbi butterfly update (compare select store unit) down to only four instruction cycles for GSM channel decoding Four internal buses and dual Enables multiple operand operations address generators and reduce memory bottlenecks 40-bit adder and two 40-bit Supports crucial parallel operations accumulators such as read & store or add & subtract, etc., in one instruction cycle Single-cycle normalization Supports floating-point arithmetic normalization and single-cycle useful in vocoding encoding 16-bit signed and 17-bit Provides for efficient implementation of unsigned multiplication voice coders Rounding and saturation Useful in GSM vocoders control in one instruction cycle New single cycle Executes common DSP tasks instructions efficiently 40-bit arithmetic logic unit Enables dual one-cycle operations (ALU) featuring a dual and supports Viterbi accelerators 16-bit configuration capability 8 auxiliary registers and TI's most advanced fixed-point DSP software stack C compiler
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