|
Related Documentation: Fact Sheet
|
High-Speed 132 Megabyte/Second PCI-to-PCI Bridge Sets New Price/Performance StandardAdvanced Features Add Capabilities, Ease Design-in Process for High Volume Applications
DALLAS (March 10, 1997) -- With the first device in the Texas Instruments (TI) family of PCI-to-PCI bridge chips, developers can take advantage of 132 megabytes per second (MB/s), maximum PCI bus performance and easily incorporate advanced capabilities to desktop personal computers, workstations, network servers, add-in cards and notebook docking stations. The new device will interface two 32-bit PCI (Peripheral Component Interconnect) buses, providing configuration flexibility not found in systems with only one bus. The PCI bus is typically limited to only four slots for add-in cards. In systems that require more than four PCI slots, one or more additional PCI buses are required. PCI-to-PCI bridges provide the interface between these extra buses. PCI-to-PCI bridges are also implemented on some multifunction add-in cards to buffer the electrical loading that the add-in card presents to the PCI bus. "Our goal was to make this device an industry leader in terms of price/performance. We were able to draw on the experience we had gained from our family of PCI-to-PC Cardä and CardBusä interface chips to achieve this goal," said Ed Agis, TI's PCIbus marketing manager. "We also set out to develop a PCI-to-PCI bridge with advanced features not found in comparable devices. These unique features make it easy for developers to add new capabilities to their PCI systems or add-in cards." The new device, designated as the PCI2030, is compatible with either 3.3V or 5V PCI signaling environments. It implements the same high-performance FIFO architecture that has been used successfully in TI's other PCI interface chips. Besides complying fully with the current versions of the PCI specification (Version 2.1) and the PCI-to-PCI bridge specification (1.0), the PCI2030 offers advanced capabilities, some of which are planned for future versions of the PCI-to-PCI bridge specification. One such feature simplifies the configuration of complex PCI-based systems by supporting both logical and physical location addresses. Reducing EEPROM on Add-In BoardsThe PCI2030 is the industry's only PCI bridge device that helps incorporates devices mask and device type registers, which can be used to help designers meet the requirements of Microsoft'sâ PC '97 specification for subsystem and vendor identification information without implementing EEPROM memory for each device on an add-in card. Designers can use the PCI2030's device mask and type registers, as well as its serial EEPROM interface, to store this information in EEPROM connected to the PCI2030, eliminating the EEPROM memory that would be used for this purpose on add-in boards. The PCI2030 also provides two additional programmable address decode windows that exceed the address granularity requirements as specified by the PCI and PCI-to-PCI bridge specifications. System designers can use these decode windows to implement memory and I/O addressing schemes, which feature much greater precision than those offered by standard PCI systems. These additional address decode windows may be especially beneficial for programming memory and input/output (I/O) windows for notebook PC docking stations and PCI add-in cards. Supporting Legacy ISA Boards and DevicesWith a feature of the PCI2030 known as subtractive decoding, PCI systems are able to effectively accommodate older ISA-based (industry standard architecture) boards or devices. PCI-based systems have difficulty handling ISA devices because the system's plug-and-play software will not assign addresses to ISA devices. Any ISA address issued on the primary PCI bus would go unclaimed if the targeted ISA device is located on the secondary or other lower-level PCI bus. The PCI2030 eliminates this problem by automatically forwarding unclaimed addresses to successive PCI buses until the ISA device is found. For portable systems, such as notebook and laptop computers, the PCI2030 is the only bridge chip to feature the clock-run capability, as defined by the PCI Mobile Design Guide, revision 1.0. Clock-run conserves battery power by dynamically adjusting the speed of the PCI bus clock to conform with the operational conditions of the bus. The PCI2030 also supports the PCI Way Serial Interrupt Protocol, which can be used to pass interrupts from devices on a notebook PC docking station to the notebook PC. Pricing and AvailabilityThe PCI2030 is packaged in a 176-pin thin quad flat pack (TQFP) carrier. The device is available now from Texas Instruments and its authorized distributors. Suggested resale pricing in quantities of 1,000 is $17 per unit. # # # Trademarks: |