Assure high-speed system throughput.

Secondary bus arbiter

Supports up to six external masters or devices on the secondary PCI bus. Additional devices can be supported by using external arbitration.

Six clock low-skew clock outputs that can be individually disabled

Minimizes clock skew to just 0.3ns, allowing designers significant propagation skew margin. Unused clock outputs may be individually disabled to reduce power consumption.

Supports the PCI Clock Run Protocol

Allows the clock speed to be dynamically changed to lower power consumption.

Programmable single- or two-tier arbitration on secondary bus

Allows high-priority devices greater access to PCI bus.

ISA mode decoding

Simplifies ISA device addressing.

Programmable latency timers

Improves system performance when slower devices are present.

Flush/acknowledge buffer signaling

Assures compatibility with other PCI-to-PCI bridge clips.

Resource locking

In multi-CPU environments, this feature prevents the CPUs from getting out of synchronization by allowing one CPU to update a shared memory resource without interruption from the other CPUs in the system.

Eight general purpose I/O (GPIO) pins

Provides designers with added flexibility and can be used to detect connections to docking stations.

PCI Way - Style Serial interrupts

Supports PCI and ISA interrupts on one pin. Increases design flexibility in docking station environments.

Parity and system error detection

Allows system to respond to a variety of error conditions.

Fabricated using CMOS process

Low power consumption.