TI Announces High-Density, Single-Chip PHY Technology for Fast Ethernet LAN Switches

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Texas Instruments Announces High-Density, Single-Chip PHY Technology for Fast Ethernet LAN Switches

DALLAS (June 2, 1997) -- Texas Instruments (TI) announces it is developing a 3.3V, quad-port, single-chip physical layer interface (PHY) device that can be used in Ethernet and Fast Ethernet networking products. The new TI ThunderSWITCH™ Quad 10/100 PHY (TNETE2104) will complement TI's TNETE2101 product (also announced today; see related news release) by offering the high density required in TI's future 10/100 LAN switches.

The new device provides four independent 10/100 PHYs in a single package using 1/6th the power of current devices. The reduced power consumption and board space requirements are both important factors in lowering overall system costs in high-performance Ethernet LAN switches.

"As TI's ThunderSWITCH solutions and the industry move toward higher LAN speeds, switch vendors want PHY devices that will support the growing number of 100 Mbps users while providing high-density access," said Robert Pace, strategic marketing manager at TI. "Like TI's TNETE2101 product, the Quad 10/100 PHY will allow switch developers to offer efficient and economical Fast Ethernet connections while continuing to support the installed base of Ethernet users."

High Density for LAN Switches

The Quad 10/100 PHY is the first device in TI's 100 Mbps ThunderSWITCH II switching platform. The device will enable networking OEMs to meet the cost/performance demands of next generation desktop switches.

Other industry-leading features for Ethernet and Fast Ethernet LAN switching applications include:

• Single 20 MHz clock for both 10 Mbps and 100 Mbps operation.
  
• Integrated filtering and equalization components enable the Quad 10/100 PHY to deliver 10/100 capabilities with minimal external components, reducing costs and use of board space.
  
• Media independent interface (MII) enables connection to both 10 Mbps and 100 Mbps networking products.
  
• Auto-negotiation automatically determines whether connected equipment is operating at half-duplex 10 Mbps up to full-duplex 100 Mbps and adjusts the communications speed accordingly.
  
• Standards compliance includes IEEE 802.3, 802.3u and JTAG.
  
• 208-pin quad flat pack (QFP) packaging offers superior heat dissipation on the chip.
  

The TI PHY architecture is designed to deliver our leadership silicon expertise in a modular, highly-integrated chip family for use in networking products that support the full range of Ethernet protocols from 10 Mbps to gigabit speeds. With the simple design of TI devices, networking equipment vendors can shorten product development times, reduce board requirements and focus on delivering value-added features.

Samples of the Quad 10/100 PHY are scheduled to be available from TI in fourth quarter 1997 with volume production planned for first quarter 1998.

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