TI Announces High-Density, Single-Chip PHY Technology for Fast Ethernet LAN Switches

TI Announces Synchronous PHY Technology for 10Base-T Ethernet Switching

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Texas Instruments Announces Synchronous PHY Technology for 10Base-T Ethernet Switching

DALLAS (June 2, 1997) -- Texas Instruments (TI) announces it is developing a synchronous physical layer interface (PHY) device that can be used in 10 Mbps Ethernet LAN switches. The new Octal Sync PHY (TNETE2008), part of the TI ThunderSWITCH family of PHY devices announced today (see related news releases), will provide eight, 10Base-T full-duplex PHYs in a single chip.

"The standards-compliant Octal Sync PHY will offer double the capacity, a smaller footprint and lower power consumption than current PHY devices," said Robert Pace, strategic marketing manager at TI. "It simplifies design requirements for developers, enabling them to produce switches with a lower cost per port, in less time."

By developing this innovative synchronous interface along with integrating eight PHYs onto a single device, TI significantly lowers the pin and die size of the device, reducing the cost and simplifying the board design. The PHYs are based on the 3.3V TNETE2101. The combination of the synchronous interface, low power and low pin count enables TI to provide a 10Base-T PHY solution in less than half the board space of current quad 10 Mbps PHY devices.

While integrating numerous PHYs onto one chip, the Octal Sync PHY synchronizes these multiple network channels, reducing the number of clocks from eight to one. This single transmit clock and receive clock for all eight ports eliminates the need for extensive clock synchronization within the switch resulting in a switch chip that is lower cost than competitive products.

"With this integrated synchronous PHY, we are able to move the clock domains away from the switch to the PHY and optimize gate usage," said Pace. "Switch manufacturers that use this PHY will produce a more competitive product."

The Octal Sync PHY is based on TI's proven ThunderSWITCH architecture, which delivers TI's silicon expertise in a modular, highly integrated chip family for use in networking products that support the full range of Ethernet protocols from 10 Mbps to gigabit speeds. By developing the PHY solutions in advanced sub-half micron digital processes, TI is able to address time to market and total cost requirements for networking OEMs.

First in a New Generation of Switching Products from TI

The Octal Sync PHY indicates TI's direction for the next generation of switching products, which will focus on helping vendors reduce the cost and chip counts of their products while simplifying board layouts. By using a synchronous interface, TI can work with vendors to reduce the total number of chips in their switching solutions.

Samples of the new chip are scheduled to be available from TI in third quarter 1997 with volume production planned for fourth quarter 1997. Planned packaging is 100-pin thin quad flat pack (TQFP).

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