Reduced Media Interface for Ethernet PHYs Enables Lower-Cost, Higher-Density Networking Devices
AMD, Broadcom, National Semiconductor and Texas Instruments Define New Specification
DALLAS (Sept. 30, 1997) -- Advanced Micro Devices (AMD) (NYSE: AMD), Broadcom Corporation, National Semiconductor Corporation (NYSE: NSM) and Texas Instruments (TI) (NYSE: TXN), today announced a jointly developed specification for a Reduced Media Independent Interface (RMII) intended for use between 10/100Mbps Ethernet physical layer interface (PHY) devices and switch silicon. By reducing the pin count and the complexity of the interface between the media access controller (MAC) and PHY components, the RMII will make it easier and less costly for system providers to build network switching solutions.
Overview of the RMII Specification
The Ethernet standard (IEEE 802.3u) defines a MII with 16 pins per port for data and control. In devices incorporating many MAC or PHY interfaces, such as switches or port-switched repeaters, the number of pins can add significant costs as port counts increase. For example, in a typical 24-port switch configuration, the RMII could reduce the number of MAC pins from 16 to six per port, for a total savings of 239* pins.
The RMII reduces PHY costs while maintaining features currently available in PHY layer silicon:
- All the functionality of 802.3u MII.
- Operation at either 10 Mbps or 100 Mbps data rates, supporting the migration towards high-speed Ethernet products.
- Implementation of a single synchronous clock reference that is sourced from the MAC to PHY (or from an external source), to simplify the clocking interface.
- Support for existing features such as full-duplex capability in switches.
The RMII is optimized for use in high-port-density interconnect devices, primarily network switch ASICs, that require independent treatment of the data paths between the MAC and PHY. The RMII is also useful for port-switched repeater ASICs that integrate more than one repeater core and provide a mapping function between PHY interfaces and internal segments.
Joint Development and Publication
The RMII specification was developed as a cooperative effort by AMD, Broadcom, National, and TI in order to meet customer demands for new PHY solutions that are available from multiple vendors. The specification was developed in cooperation with leading network equipment providers.
The published RMII specification document is available now at AMD's website http://www.amd.com, Broadcom's website http://www.broadcom.com, National's website http://www.national.com/appinfo/lan, and TI's website 
http://www.ti.com/sc/docs/network/nbuhomex.htm.
*One pin has been reserved for clock function.
Related Documentation: