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Application Specific Integrated Circuits Application Specific Integrated Circuits - Product Information Texas Instruments is First to Merge Standard Cell Cost-Effectiveness and Gate Array Time-to-Market in a Single Chip GS30 TImeCell™ Unified ASIC Architecture
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Texas Instruments is First to Merge Standard Cell Cost-Effectiveness and Gate Array Time-to-Market in a Single ChipTI's New 0.13-µm TImeCell™ Architecture Drives ASIC Integration to Multimillion-Gate System LevelsDALLAS (July 27, 1998) -- Designers of application-specific integrated circuits (ASICs) will soon be able to enjoy the best of both standard cells and gate arrays, thanks to a new class of ASIC products announced today by Texas Instruments (TI). TI's new TImeCell Unified ASIC Architecture is the first to fully merge both standard cell and gate array technology on the same chip, giving designers the cost efficiencies of standard cells, together with the fast time-to-market advantages of gate arrays. TImeCell's powerful combination of the two ASIC technologies gives designers the flexibility they need to build multimillion-gate, single-chip systems. Designers no longer have to choose between the greater density and lower per-unit costs of standard cells, and the rapid turnaround and flexibility of gate arrays. "Fast turnaround time, combined with high performance and low unit cost, are three of the most important elements of an ASIC offering," said Ron Collett, President of Collett International, Inc. "The market has always wanted silicon suppliers to combine the advantages of gate array and standard cell technologies." "TI gate arrays have long been used by Nortel for time-to-market. With TImeCell, Nortel will be able to take advantage of standard cell density while maintaining the advantages of gate array," said Dino Diperna, Director, High Capacity Product Development, Nortel. "In recent years, the ASIC market has moved increasingly toward the density of deep submicron standard cells," said David Shepard, Worldwide Marketing Director, ASIC Products, Texas Instruments. "However, designers still need the faster prototyping and ease of modification offered by gate arrays. TimeCell gives designers the best of both worlds in a single product." The TImeCell architecture will first be available in TI's GS30 ASIC product family, which will be built using TI's advanced 0.13-µm Leffective (Leff) TImeline II™ process technology. The powerful combination of the new architecture with an advanced 0.13-µm process will make system-level integration of multimillion gate densities a reality. A New Approach to ASIC Design Today, most complex ASICs are developed by taking an already proven design and adding new functionality. TImeCell allows designers to pack the proven sections of their designs into ultra-dense standard cell logic, while creating new logic functions in gate arrays. Using this approach reduces layout and prototype fab cycle time by more than 50 percent over standard cell and enables users to make changes in their design up until the last moment. While giving designers more flexibility at the silicon level, TImeCell will also enable a whole new design approach. Designers will be able to combine sections of customized logic with a variety of system-level blocks, including DSP cores, peripherals, RAMs and standard processing units. By building the reused parts in standard cell and the customized blocks in gate array logic, designers will be able to quickly spin off derivative products from a common silicon base. This approach is ideal in areas such as wireless communications, where products are differentiated by including different feature sets. "The primary factor that has slowed the development of true system-level chips is the inability of designers to design very complex ASICs and still meet the continuously shrinking time-to-market windows," said Shepard. "Designers have been forced to sacrifice complexity, performance or development time in order to meet their goals." "TImeCell addresses this issue by giving designers ultimate flexibility and efficiency. The full performance capability of the process is maintained while achieving best-in-class cycle times and gate density. In addition, the ability to integrate industry-leading DSP cores and a full suite of reusable blocks give designers everything they need to make system-level integration a reality." Applications The GS30 TImeCell family has been adapted to support a wide range of applications. Low-power products such as wireless phones can take advantage of the technology's low power dissipation and its ability to integrate a wide range of processors including TI's leadership DSPs and the ARM microcontroller. Designers of high-performance systems such as SDH/SONET and gigabit networking switches will welcome access to TI's full range of high-performance macros, including its gigabit high-speed interfaces and support macros. Availability TI will take designs on its 0.13-µm product in third quarter 1998 and expects to support prototyping in first half 1999. Production is expected in second half 1999. The TImeCell architecture is also planned to be available in TI's existing 0.18-µm ASIC product in the same timeframe.
More information about TI's TImeCell architecture and other ASIC products is available on the World Wide Web at
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