Application Specific Integrated Circuits - Product Information

Texas Instruments is First to Merge Standard Cell Cost-Effectiveness and Gate Array Time-to-Market in a Single Chip

GS30 TImeCell™ Unified ASIC Architecture

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• Fully merged gate array and standard cell architecture
• Size and location of gate array regions are fully user definable
• Gate array region performance equal to that of standard cell
• Advanced five-level, ultra-fine-pitch metal TImeline™ process - 0.13 µm (Leff)
• 2X density increase over 0.18µm processes
• Extremely high density SRAM
• Multi-gigabit serial link transceiver technology
• 0.8- to 1.65-volt cores; 0.8- to 3.6-volt I/Os
• Low power - 0.018 µW/MHz/gate for 1.5-volt core
• Multimillion-gate, single-chip system enabler
• Ability to integrate TMS320 DSPs, ARM™ 32-bit RISC MCUs, analog functions
• Broad I/O Options:
• LVCMOS/LVTTL, 3V tolerant, 3.6V failsafe, 0.8v - 3.6v signaling, LVDS, HSTL, CML, PCI, ATA-66
• VHDL, IEEE 1076.4-95/VITAL '95, and Verilog
• Power Management methodologies (clock tree synthesis, clock skew management - 125 ps skew)
• Static Timing Analysis (STA) sign-off
• SubChip™ design capabilities that support reuse
• Simultaneous optimization for timing, area and power using Synopsys Power Compiler™
• Industry Leading Compiled Memory:
  • 1M single-port SRAM, two-port SRAM, dual-port SRAM, three-port SRAM, ROM, CAM
• Broad Packaging Options:
  • Tape BGA
  • MicroStar™ ball grid array (BGA)
  • Quad flatpack (QFP)
  • Thin quad flatpack (TQFP)
  • Plastic QFP (PQFP)
  • Ceramic BGA (flip-chip)
  • Laminate BGA (flip-chip)
  • Multi-layer BGA

Trademarks:
SubChip, TImeCell, TImeline and MicroStar are trademarks of Texas Instruments Incorporated.
Power Compiler is a trademark of Synopsys, Incorporated.
ARM is a trademark of ARM Limited.