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Scalable 1.0 to 2.5 Gigabit per Second SERDES Transceiver ASIC Core Application Specific Integrated Circuits Texas Instruments Delivers World's First 2.5 Gbps Transceiver Core for CMOS ASICs 2.5Gbps SERDES ASIC Core Analyst Quote Sheet
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2.5Gbps SERDES ASIC Core Analyst Quote Sheet
"Networking vendors' demand for less complex, higher performance and lower cost switching architectures is being realized in TI's 2.5 Gbps SERDES ASIC," said Shannon Pleasant, Networking IC Analyst with Cahners In-Stat Group. "TI's unparalleled SERDES ASIC core represents a milestone for today's high performance networks."
Shannon Pleasant
"TI's new CMOS 2.5 Gbps SERDES ASIC core provides increased throughput, reduces pin count, and requires less power than existing solutions. This is a significant step toward solving a major bottleneck in packet switch architectures. TI's design considerations, such as utilizing the standard cell CMOS process as well as including unique self-test functions, should result in a product that is very cost effective and highly manufacturable."
Bob Merritt
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