Architecture

TI's innovative new VelociTI architecture pushes the envelope with its extraordinary processing power, ease-of-use and cost savings.

VelociTI™ an advanced Very Long Instruction Word (VLIW) architecture provides extremely simple and cost-effective access to the power of on-chip, instruction-level parallelism.

Using TI's industry-leading semiconductor processes and revolutionary compiler technology, VelociTI is the new architecture of choice for benchmark performance and cost-effective DSP-based designs.

Traditionally, the advantages associated with VLIW architectures were often difficult to obtain. A lack of sophisticated code generation tools meant that programmers were required to spend many hours optimizing their code for performance only to find these optimizations were largely negated by cumbersome and unwieldy code sizes.

The 'C6x generation eliminates these drawbacks with VelociTI, a highly parallel and independent architecture that emphasizes software-based flexibility through the industry's most efficient C compiler and the industry's first Assembly Optimizer. For designers, the direct translation is faster time-to-market with highly integrated and differentiated products.

"The beauty of this advanced VLIW architecture is really its elegant simplicity,"said Ray Simar, TI's 'C6x chief architect and program manager. "It moves complexity from the hardware to the compiler, allowing a simpler yet faster processor at less cost that is easy to program."

VelociTI's advanced features include instruction packing, conditional instructions, variable-width execution packets and pre-fetched branching, all of which eliminate the problems associated with historical VLIW implementations. Architectural streamlining and compiler intelligence that implements instruction scheduling at compile time allow the 'C6201 to be fabricated using only 550,000 logic transistors. In contrast, Intel's Pentium™ requires about 5 million logic transistors.

The TMS320C6x pushes the envelope with 1600 MIPS to allow a file to download in five seconds instead of today's 10 minutes.

Key features
Benefits

Advanced VLIW CPU with eight functional units including two multipliers and six arithmetic units Executes up to eight instructions per cycle for up to 10 times the performance of typical DSPs. Allows designers to develop highly effective RISC-like code for fast development time.

Instruction packing Code size equivalence for eight instructions executed serially or in parallel. Reduces code size, program fetches and power consumption.

100-percent conditional instructions Reduces costly branching. Increases parallelism for higher sustained performance.

Code executes as programmed on highly independent functional units Industry's most efficient C compiler on DSP benchmark suite and DSP industry's first Assembly Optimizer for fast development time.

8/16/32-bit data support Efficient memory support for a variety of applications.

40-bit arithmetic options Extra precision for vocoders and other computationally intensive applications.

Saturation and normalization Supports key arithmetic operations.

Bit-field manipulation and instruction: extract, set, clear, bit counting Supports common operation found in control and data manipulation applications.

1 Mbit on-chip memory (512K bits program, 512K bits data) Fast algorithm execution with fewer components per system.

32-bit external memory interface supports SDRAM, SBSRAM, and SRAM High-speed connections to external memory for maximum sustained performance.

Two enhanced buffered serial ports (EBSP) Glueless interface to high bandwidth telecommunications trunks. Provides high speed interprocessor communication.

16-bit host access port Host processor access to on-chip data memory.

Two data memory access (DMA) channels with bootloading capability Efficient access to external memory/peripherals while minimizing CPU interrupts.

Flexible Phase-Locked-Loop (PLL) clock generator Multiplies external clock rate by two or four for maximum CPU performance.

352-lead ball grid array (BGA) package Ultra-thin package supports industry trend for higher integration and minimized board space.

Key features	Benefits
Advanced VLIW CPU with eight functional units including two multipliers and six arithmetic units	Executes up to eight instructions per cycle for up to 10 times the performance of typical DSPs. Allows designers to develop highly effective RISC-like code for fast development time.
Instruction packing	Code size equivalence for eight instructions executed serially or in parallel. Reduces code size, program fetches and power consumption.
100-percent conditional instructions	Reduces costly branching. Increases parallelism for higher sustained performance.
Code executes as programmed on highly independent functional units	Industry's most efficient C compiler on DSP benchmark suite and DSP industry's first Assembly Optimizer for fast development time.
8/16/32-bit data support	Efficient memory support for a variety of applications.
40-bit arithmetic options	Extra precision for vocoders and other computationally intensive applications.
Saturation and normalization	Supports key arithmetic operations.
Bit-field manipulation and instruction: extract, set, clear, bit counting	Supports common operation found in control and data manipulation applications.

1 Mbit on-chip memory (512K bits program, 512K bits data)	Fast algorithm execution with fewer components per system.
32-bit external memory interface supports SDRAM, SBSRAM, and SRAM	High-speed connections to external memory for maximum sustained performance.
Two enhanced buffered serial ports (EBSP)	Glueless interface to high bandwidth telecommunications trunks. Provides high speed interprocessor communication.
16-bit host access port	Host processor access to on-chip data memory.
Two data memory access (DMA) channels with bootloading capability	Efficient access to external memory/peripherals while minimizing CPU interrupts.
Flexible Phase-Locked-Loop (PLL) clock generator	Multiplies external clock rate by two or four for maximum CPU performance.
352-lead ball grid array (BGA) package	Ultra-thin package supports industry trend for higher integration and minimized board space.