App Report

The TMS320C54x accumulators
39-32	31-16	15-0

G	L	H

Guard bits	High-order bits	Low-order bits
The guard bits are used as headmargin for computations allowing some overflow in iterative calucations.

Extended precision IIR filter design on the TMS320C54x DSP: This application note presents methods of achieving a good compromise in accuracy when carrying out extended-precision multiplications for the implementation of IIR (Infinite Impulse Response) filters. The TMS320C54x devices are 16-bit, fixed-point processors and have several features that help to perform extended-precision computation efficiently. The TMS320C54x CPU has a 17x17-bit hardware multiplier coupled to a 40-bit dedicated adder. The advantage of this multiplier is that it can multiply two unsigned numbers or two signed numbers as well as signed/unsigned numbers [4]. The 'C54x has two accumulators called A and B that can be configured as the destination registers for the multiplier/adder unit. Each accumulator is split into three parts as shown above.

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