Inside

• Simplify designs with integrated 3-V LDO and supply voltage supervisor
• Lowest distortion 1.5 W stereo audio amplifier
• 8-Bit, 20 MSPS ADC with 4-volts of analog input range
• TI expands family of 3.3-V LVDS devices
• Ultra fast voltage comparators
• 20_Bit stereo A/D and D/A offers professional audio

Product Features

• 227 Mbytes/sec
• Low EMI and low power (250 mW typ)
• Enhanced Replacement for TTL buses
• 28:4 (SN75LVDS83) or 21:3 (SN75LVDS84/85) data channel compression
• 3:21 data channel expansion with SN75LVDS86 receiver
• Single 3.3-V supply with 5-V tolerant inputs
• Characterized for operation from 0°–70°C

The addition of the SN75LVDS83 through SN75LVDS86 to the previously released SN75LVDS81 and SN75LVDS82 expands TI’s first generation FlatLink^TM family of products. All of the products are designed to address the electrical noise and mechanical issues resulting from moving large amounts of binary data with traditional TTL signals. The electrical noise and electromagnetic interference (EMI) are reduced significantly by using low-voltage differential signaling between the transmitter and receiver. The width of the bus is reduced by employing serialization and then deserialization of the data.

FlatLink was developed to transfer display data and control signals from portable computer video display processor to flat-panel displays. Previously, the data interchange was accomplished through a wide synchronous parallel data transfer using single-ended signals. With increased resolution and color requirements, the necessary data transfer rate can not be achieved without increasing the bus width or EMI to an unacceptable level.

Although designed to address a specific application problem, FlatLink can be used to improve the performance of any wide parallel single-ended synchronous data connection.

These products operate with a single 3.3-V supply for lower power consumption. High data throughput is achieved by an internal 7x PLL which operates from a reference clock from 31 to 67.

The SN75LVDS83 allows the user to select either positive-going or negative-going clock edge triggering. The ‘LVDS83 has four 7-bit parallel-to-serial shift registers, PLL clock synthesizer and five ‘LVDS output buffers. The ‘LVDS84 and ‘LVDS85 are similar in architecture, but drop one of the parallel-to-serial shift registers and one output buffer, and fit in a 48-pin instead of the 56-pin package. The ‘LVDS86 is a companion receiver to the ‘LVDS84 and ‘LVDS85 transmitters, with three serial-to-parallel shift registers, PLL clock synthesizer and four ‘LVDS input buffers.

FlatLinks family of devices are compatible to existing competitive solutions in the market. Devices are available in 48-pin and 56-pin TSSOP.

• SN75LVDS83DGG