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Important announcement about TI Speech product line changes
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Precautions for software development the TSP50C04/06/13/14/19
The following devices were developed after the EVM50C1x emulator and it is important to note that the program code should account for issues which could potentially allow programs to run without problems on the emulator system but fail on the production silicon.
Devices affected:
- TSP50C04
- TSP50C06
- TSP50C13
- TSP50C14
- TSP50C19
- The EVM50C1x and EMU50C1x have 128 RAM locations. The TSP50C04/06/13/14/19 devices only have 64 RAM locations. No program targeted for these devices should use RAM locations above 63 decimal.
- The B port on the EVM50C1x and EMU50C1x is 8 bits wide. The B port on the TSP50C04/06/10/11/13/14/19 is only 2 bits wide. Since the upper 6 bits of the B port actually exist on the emulator, setting the port registers to specific values the rereading the register will read the value which was written. On the actual device, rereading the register will result in
garbage being read. The most common manifestation of this problem is that the input port is read and the program assumes that the upper bits are cleared to zero. When an ANEC or AGEC command is used to decode the input value, an incorrect result will be obtained.
Note that this issue exists on all TSP50C0x/1x devices except for the TSP50C12. The TSP50P11 can be used to test device functionality against this issue.
- The internal oscillator on the TSP50C04/06/13/14/19 devices has a pronounced voltage and temperature coefficient. The crystal oscillator on the emulator may mask problems in codes which are sensitive to the precise clock frequency.
The emulator or the MSD50C1x board may be externally driven using a function generator to test code for sensitivity to clock frequency.
- The TSP50C19 incorporates a paged program address scheme which is inconsistent with the rest of the family. If there is any possibility that a code will in the future be ported to the TSP50C19, then care should be taken that bits B2 and B3 of the B port are not modified. Bits B0 and B1 should be set and cleared using the ORCM and ANDCM instructions rather than broadside load (e. g., TAM, TAMD, etc.) if compatibility with the TSP50C19 is desired.
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