 Key Features | Benefits
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| Advanced VLIW CPU with eight functional units including two multipliers and six arithmetic units
| Up to 10 times the performance of typical DSPs; Allows designers to develop highly effective RISC-like code for fast development time
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| Instruction packing | Code size equivalence for eight instructions executed serially or in parallel; Reduces code size, program fetches, and power consumption
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| 100 percent conditional instructions | Reduces costly branching; Increases parallelism for higher sustained performance.
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| Code executes as programmed on highly independent functional units
| benchmark suite and DSP industry's first assembly optimizer for fast development time.
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| 8/16/32-bit data support | Efficient memory support for a variety of applications.
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| 40-bit arithmetic options | Extra precision for vocoders and other computationally intensive applications.
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| Saturation and normalization | Supports key arithmetic operations.
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Bit-field manipulation and instruction:
extract, set, clear, bit counting
| Supports common operation found in control and data manipulation applications.
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1Mbit on-chip memory
(512K bits program, 512K bits data)
| Fast algorithm execution with fewer components per system.
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| 32-bit glueless external memory interface supports SDRAM, SBSRAM and SRAM
| High speed connections to external memory for maximum sustained performance.
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| Two enhanced buffered serial ports (EBSP) |
Glueless interface to high bandwidth telecommunications trunks; Provides high speed interprocessor communication
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| 16-bit host access port | Host processor access to on-chip data memory.
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| Two data memory access (DMA) channels with bootloading capability
| Efficient access to external memory/peripherals while minimizing CPU interrupts.
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| Flexible Phase-Locked-Loop (PLL) clock generator
| Multiplies external clock rate by two or four for maximum CPU performance.
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| 352-lead ball grid array (BGA) package |
Ultra thin package supports industry trend for higher integration and minimizing board space
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