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Scalable 1.0 to 2.5 Gigabit per Second SERDES Transceiver ASIC Core Application Specific Integrated Circuits Texas Instruments Delivers World's First 2.5 Gbps Transceiver Core for CMOS ASICs 2.5Gbps SERDES ASIC Core Analyst Quote Sheet
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Texas Instruments Delivers World's First 2.5 Gbps Transceiver Core for CMOS ASICsEnables 160 Gbps Switching Bandwidth on a Single ASIC, With Lowest Power Consumption
Available today, the 2.5 Gbps SERDES ASIC core offers the possibility of building switch/routers with an order-of-magnitude increase in bandwidth over today's high performance switch/routers, without the need for discrete SERDES and ASIC packaging with thousands of pins. For example, TI has shown that switch architectures with at least 512 Gbps are possible with this technology by simply integrating high-speed SERDES to a crossbar architecture. This replaces traditional wide bus architectures and costly board, connector and semiconductor packaging technology. With TI's new SERDES core, designers can implement a lower cost, more simple solution that provides up to four times the performance of alternatives. In addition, many high-performance switching and routing systems use 1 Gbps to 1.25 Gbps catalog products today. TI's 2.5 Gbps SERDES ASIC core is compatible with these products and auto-scalable from 1 Gbps to 2.5 Gbps, enabling the system designer to reduce costs of existing systems and simultaneously implement performance upgrades. It is also optimized for power, area and signal integrity across a backplane connector, and copper and optical interfaces. At 2.5 Gbps, the SERDES core typically consumes 200mW -- which is 70 percent less power than alternatives. "This SERDES ASIC core from TI allows us to integrate catalog SERDES transceivers with 150,000 gates and memory," stated Abbot Gilman, Chief Operating Officer at Broadband Access Systems. "To switch at line-speed, our system required 1.6 Gbps performance. TI's solution gave us the flexibility not available with catalog products and other ASIC solutions. In addition, since TI's core is capable of 2.5Gbps, we can upgrade the performance of the system as needed with the same core." "The I/O that feeds data to the switch fabric is a bottleneck faced by all packet switch designers," stated Brett Butler, director of core networking products in TI's ASIC group. "There are brute-force approaches on the market that utilize massively parallel architectures. But these have limited scalability. This 2.5 Gbps SERDES ASIC core provides a more simple, scalable solution to the system designer." TI's SERDES ASIC core supports full-duplex data transfer with fully integrated clock generator and clock recovery modules. Input and output signal levels have been defined to be compatible with Fibre Channel specifications. TI's 2.5 Gbps SERDES ASIC core also incorporates a novel self-test function that allows the 2.5 Gbps performance to be tested on standard digital ASIC production test equipment. This feature streamlines the development of new products. "By offering 160 Gbps of bandwidth on a single ASIC, TI is first to deliver such a significant advance in system integration," stated Martin Izzard, director of ASIC advanced development at TI. "TI has been demonstrating this performance level and providing samples to customers for over 10 months. Our customers can now take advantage of this breakthrough to offer their customers a more scalable system." The 2.5 Gbps SERDES ASIC core is currently available in TI's TSC5000 0.25-micron standard cell ASIC family and is expected to be available in TI's TSC6000 0.18-micron standard cell ASIC family by the end of this year. Designs integrating the core are being accepted for production.
More information about TI's 2.5 Gbps SERDES ASIC core is available on the World Wide Web at http://www.ti.com/sc/docs/asic/modules/serdes.htm. Information on the original 2.5 Gbps transceiver technology (announced in June, 1998) is available at # # #
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